To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were iden...To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.展开更多
High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-...High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-IPEM）, consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.展开更多
The physics package of a chip-scale atomic clock （CSAC） has been successfully realized by integrating vertical cavity surface emitting laser （VCSEL）, neutral density （ND） filter, λ/4 wave plate, 87Rb vapor cell...The physics package of a chip-scale atomic clock （CSAC） has been successfully realized by integrating vertical cavity surface emitting laser （VCSEL）, neutral density （ND） filter, λ/4 wave plate, 87Rb vapor cell, photodiode （PD）, and magnetic coil into a cuboid metal package with a volume of about 2.8 cm3. In this physics package, the critical component, 87Rb vapor cell, is batch-fabricated based on MEMS technology and in-situ chemical reaction method. Pt heater and thermistors are integrated in the physics package. A PTFE pillar is used to support the optical elements in the physics package, in order to reduce the power dissipation. The optical absorption spectrum of 87Rb D1 line and the microwave frequency correction signal are successfully observed while connecting the package with the servo circuit system. Using the above mentioned packaging solution, a CSAC with short-term frequency stability of about 7 × 10^-10τ-1/2 has been successfully achieved, which demonstrates that this physics package would become one promising solution for the CSAC.展开更多
Stacked chip scale package(SCSP) attracts more and more attentions in advanced packages application with light weight,thin and small size,high reliability,low power and high storage capability.However,more and more ph...Stacked chip scale package(SCSP) attracts more and more attentions in advanced packages application with light weight,thin and small size,high reliability,low power and high storage capability.However,more and more physical and electrical issues being caused by package-induced stress in SCSP were reported recently.The effect of structural factors,including die thickness,die attach film thickness,die attach film type,and spacer size on package induced stress,was investigated.Analyses were given based on simulation results and provide important suggestion for package design.展开更多
基金Projects(51475072,51171036)supported by the National Natural Science Foundation of China
文摘To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.
基金Fok Ying Tung Education Foundation(No.91058)the Natural Science Foundation of High Education Institutions of Jiangsu Province(No.08KJD470004)Qing Lan Project of Jiangsu Province of 2008
文摘High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-IPEM）, consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.
基金supported by the Knowledge Innovation Project of Chinese Academy of Sciences(Grant No.KGCX2-YW-143)
文摘The physics package of a chip-scale atomic clock （CSAC） has been successfully realized by integrating vertical cavity surface emitting laser （VCSEL）, neutral density （ND） filter, λ/4 wave plate, 87Rb vapor cell, photodiode （PD）, and magnetic coil into a cuboid metal package with a volume of about 2.8 cm3. In this physics package, the critical component, 87Rb vapor cell, is batch-fabricated based on MEMS technology and in-situ chemical reaction method. Pt heater and thermistors are integrated in the physics package. A PTFE pillar is used to support the optical elements in the physics package, in order to reduce the power dissipation. The optical absorption spectrum of 87Rb D1 line and the microwave frequency correction signal are successfully observed while connecting the package with the servo circuit system. Using the above mentioned packaging solution, a CSAC with short-term frequency stability of about 7 × 10^-10τ-1/2 has been successfully achieved, which demonstrates that this physics package would become one promising solution for the CSAC.
文摘Stacked chip scale package(SCSP) attracts more and more attentions in advanced packages application with light weight,thin and small size,high reliability,low power and high storage capability.However,more and more physical and electrical issues being caused by package-induced stress in SCSP were reported recently.The effect of structural factors,including die thickness,die attach film thickness,die attach film type,and spacer size on package induced stress,was investigated.Analyses were given based on simulation results and provide important suggestion for package design.
