Effect of F doping on capacitance-voltage characteristics of SiCOH low-k films metal-insulator-semiconductor

This paper investigates the capacitance-voltage （C-V） characteristics of F doping SiCOH low dielectric constant films metal-insulator-semiconductor structure. The F doping SiCOH films are deposited by decamethylcyclopentasilox-ane [DMCPS） and trifluromethane （CHF3） electron cyclotron resonance plasmas. With the CHF3/DMCPS flow rate ratio from 0 to 0.52, the positive excursion of C-V curves and the increase of fiat-band voltage VFB from -6.1 V to 32.2V are obtained. The excursion of C-V curves and the shift of VFB are related to the change of defects density and type at the Si/SiCOH interface due to the decrease of Si and O concentrations, and the increase of F concentration. At the CHF3/DMCPS flow rate ratio is 0.12, the compensation of F-bonding dangling bond to Si dangling bond leads to a small VFB of 2.0V.

The physical process analysis of the capacitance-voltage characteristics of AlGaN/AlN/GaN high electron mobility transistors

This paper deduces the expression of the Schottky contact capacitance of AlGaN/A1N/GaN high electron mobility transistors （HEMTs）, which will help to understand the electron depleting process. Some material parameters related with capacitance-voltage profiling are given in the expression. Detailed analysis of the forward-biased capacitance has been carried on. The gate capacitance of undoped AlGaN/AlN/GaN HEMT will fall under forward bias. If a rising profile is obviously observed, the donor-like impurity or trap is possibly introduced in the barrier.

Physically based analytical model for plateau in gate C-V characteristics of strained silicon pMOSFET

A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.The extracted parameters from our model were tOX=20 nm,ND=1×1016cm 3,tSSi=13.2 nm,consistent with the experimental values.The results show that the simulation results agree with experimental data well.It is found that the plateau can be strongly affected by doping concentration,strained-Si layer thickness and mass fraction of Ge in the SiGe layer.The model has been implemented in the software for strained silicon MOSFET parameter extraction,and has great value in the design of the strained-Si/SiGe devices.

A new algorithm based on C-V characteristics to extract the epitaxy layer parameters for power devices with the consideration of termination

Doping concentration and thickness of an epitaxy layer are the most essential parameters for power devices.The conventional algorithm extracts these two parameters by calculating the doping profile from its capacitance-voltage(C-V)characteristics.Such an algorithm treats the device as a parallel-plane junction and ignores the influence of the terminations.The epitaxy layer doping concentration tends to be overestimated and the thickness underestimated.In order to obtain the epitaxy layer parameters with higher accuracy,a new algorithm applicable for devices with field limited ring(FLR)terminations is proposed in this paper.This new algorithm is also based on the C-V characteristics and considers the extension manner of the depletion region under the FLR termination.Such an extension manner depends on the design parameters of the FLR termination and is studied in detail by simulation and modeling.The analytical expressions of the device C-V characteristics and the effective doping profile are derived.More accurate epitaxy layer parameters can be extracted by fitting the effective doping profile expression to the C-V doping profile calculated from the C-V characteristics.The relationship between the horizontal extension width and the vertical depth of the depletion region is also acquired.The credibility of the new algorithm is verified by experiments.The applicability of our new algorithm to FLR/field plate combining terminations is also discussed.Our new algorithm acts as a powerful tool for analyses and improvements of power devices.

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al_2O_3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.

Electrical characteristics of MOS capacitor with HfTiON gate dielectric and HfTiSiON interlayer

The paper reports that Hfrio dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O2 ambience, followed by an annealing in different gas ambiences of N2, NO and NH3 at 600℃ for 2 min. Capacitancevoltage and gate-leakage properties are characterized and compared. The results indicate that the NO-annealed sample exhibits the lowest interface-state and dielectric-charge densities and best device reliability. This is attributed to the fact that nitridation can create strong Si≡N bonds to passivate dangling Si bonds and replace strained Si-O bonds, thus the sample forms a hardened dielectric/Si interface with high reliability.

Determination of capacitance-voltage characteristics of organic semiconductor devices by combined current-voltage and voltage decay measurements

We present in this paper a new method,based on measurements of conventional direct current-voltage(I-V) characteristics and transient voltage-time(V-t) characteristics during the discharge process,for determining capacitance-voltage(C-V) characteris-tics of organic semiconductor devices.Derivatives of I-V and V-t,dI/dV and dV/dt,are related with C by a simple formula C=-V(dI/dV)/(dV/dt)The validity of the method is confirmed by experimental data measured from a set of single-organic-layer devices with different layer thicknesses.

High-frequency capacitance-voltage characteristics of the heterogeneous structure based on the model of spherical semiconductor particles in a dielectric

The dependence of the parameters of the capacitance effect in heterogeneous dispersed two-component structures based on semiconductors from the bulk fraction of the semiconductor component is modeled.The used method for determining the changes of the energy bands bending on the surface of the spherical semiconductor particle by applying dc electric field allowed to calculate the changes of the dipole moment and effective(taking into account the polarization of the free charge)dielectric constant of this semiconductor particle.This result allowed to use the known models of the dielectric constant of two-component structures for the description of the capacitance field effect in the heterogeneous structures.The relations allowing to estimate the value of the bulk donor concentration in the semiconductor component of the matrix of the heterogeneous system and the statistical mixture have been obtained.The approbation of the obtained calculation relations to evaluate the donor concentration in the ZnO grains of zinc oxide varistor ceramics leads to the correct values that are consistent with estimates of other methods and models.It is established that the sensitivity of the relative dielectric constant to the applied dc electric field is dependent on the bulk fraction of the semiconductor particles in the heterogeneous structures.The bulk fraction of the semiconductor particles significantly affects on the dielectric constant beginning with the values from
0:8 for matrix systems and
0:33 for statistical mixtures.

C-V characteristics of piezotronic metal-insulator-semiconductor transistor

Third generation semiconductors for piezotronics and piezo-phototronics,such as Zn O and Ga N,have both piezoelectric and semiconducting properties.Piezotronic devices normally exhibit high strain sensitivity because strain-induced piezoelectric charges control or tune the carrier transport at junctions,contacts and interfaces.The distribution width of piezoelectric charges in a junction is one of important parameters.Capacitance-voltage(C-V)characteristics can be used to estimate the distribution width of strain-induced piezoelectric charges.Piezotronic metal–insulator-semiconductor(MIS)has been modelled by analytical solutions and numerical simulations in this paper,which can serve as guidance for C-V measurements and experimental designs of piezotronic devices.

Charge storage characteristics of Ni nanocrystals formed by synchronous crystallization

The rapid thermal annealing （RTA） nano-crystallization method is widely used in the metal nanocrystal fabrication process. However, the high temperature （usually 600 900 ℃） in the RTA process will worsen the per- formance and reliability of devices. A novel method has been proposed to grow metal nanocrystal by synchronous in situ nano-crystallization of metal thin film （SINC）, which is able to resolve the problems mentioned above. Com- pared with Ni nanocrystals （NCs） formed by RTA, Ni NCs prepared by SINC can obtain more energy to crystallize, and its crystallization temperature is greatly reduced. A large memory window （2.78 V） was observed for Ni NCs deposited by SINC at 300 ℃. However, the largest window is only 1.26 V for Ni NCs formed by RTA at 600 ℃. A large change （from 0.20 to 4.59 V） of the memory window was observed while the operation voltage increased from 0 to 4-10 V, which is due to an occurrence of strong carrier trapping in Ni NCs. Flat-band voltage shift rapidly increases to its saturation value, which indicates that electron/hole trapping in Ni NCs mainly occurs at the initial stage of the program/erase process. A theoretical model was proposed to characterize the charging and discharging processes.

Aluminum Nitride Films Fabricated by Mid-frequency Magnetron Sputtering

Aluminum nitride films were prepared by mid-frequency magnetron sputtering on Si (111) substrate. The grown films were characterized by X-ray diffraction(XRD), scanning electron microscopy(SEM) and X-ray photoelectron spectroscopy(XPS) to obtain the structural and the chemical information. The polycrystalline thin films were in a hexagonal wurtzite structure having a (002) preferred orientation, along which the columnar grain structure was found. XPS study revealed the presence of oxygen and carbon contaminations, as well as the Al-rich nature of the film. Anomalous C-V characteristics of Al/AlN/n-Si capacitors were studied. The measured C-V curves show rolloffs in the accumulation region and voltage stresses cause both horizontal and vertical shifts of the C-V curves. These anomalous behaviors are mainly due to the large current conduction and the charge trapping in the Al-rich AlN layer.

Optimization of terahertz monolithic integrated frequency multiplier based on trap-assisted physics model of THz Schottky barrier varactor

The optimization of high power terahertz monolithic integrated circuit (TMIC) is systemically studied based on the physical model of the Schottky barrier varactor (SBV) with interface defects and tunneling effect. An ultra-thin dielectric layer is added to describe the extra tunneling effect and the damping of thermionic emission current induced by the interface defects. Power consumption of the dielectric layer results in the decrease of capacitance modulation ration (Cmax/Cmin), and thus leads to poor nonlinear C–V characteristics. The proposed Schottky metal-brim (SMB) terminal structure could improve the capacitance modulation ration by reducing the influence of the interface charge and eliminating the fringing capacitance effect. Finally, a 215 GHz tripler TMIC is fabricated based on the SMB terminal structure. The output power is above 5 mW at 210–218 GHz and the maximum could exceed 10 mW at 216 GHz, which could be widely used in terahertz imaging, radiometers, and so on. This paper also provides theoretical support for the SMB structure to optimize the TMIC performance.

Analysis on electrical transport characteristic of 8-hydroquinoline aluminum film

The current_voltage and capacitance_voltage characteristic of the organic single_layered electroluminescent diode utilizing 8_hydroquinoline aluminum as active layer have been measured under bias ranging from -5 V to 28 V in this work. A simple model for charge transport process of 8_hydroquinoline aluminum layer is proposed to illuminate the conductivity characteristic of the diode.

Performance analysis of 20 nm gate-length In_(0:2)Al_(0:8)N/GaN HEMT with Cu-gate having a remarkable high I_(ON)/I_(OFF)ratio

： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.

Effect of post oxidation annealing in nitric oxide on interface properties of 4H-SiC/SiO_2 after high temperature oxidation

The interface properties of 4H-SiC metal oxide semiconductor （MOS） capacitors with post-oxidation annealing （POA） in nitric oxide （NO） ambient after high temperature （1300 ℃） oxidation have been investigated using capacitance-voltage （C V） measurements. The experimental results show that the interface states density （Dit） can be obviously decreased by the POA in NO ambient （NO-POA） and further reduced with increasing POA temperature and time. In the meantime significant reduction of the interface states density and oxidation time can be achieved at the higher thermal oxidation temperature, which results in the better oxide MOS characteristics and lower production costs. The dependence of Dit on POA temperature and time has been also discussed in detail.

Fabrication of a novel MOS diode by indium incorporation control for microelectronic applications

Control of the electronic parameters on a novel metal–oxide–semiconductor（MOS）diode by indium doping incorporation is emphasized and investigated.The electronic parameters,such as ideality factor,barrier height（BH）,series resistance,and charge carrier density are extracted from the current–voltage（I–V）and the capacitance–voltage（C–V）characteristics.The properties of the MOS diode based on 4%,6% and 8% indium doped tin oxide are largely studied.The Ag/SnO2/nSi/Au MOS diode is fabricated by spray pyrolysis route,at 300℃ from the In-doped SnO2layer.This was grown onto n-type silicon and metallic（Au）contacts which were made by thermal evaporation under a vacuum@10^-5 Torr and having a thickness of 120 nm and a diameter of 1 mm.Determined by the Cheung-Cheung approximation method,the series resistance increases（334–534Ω）with the In doping level while the barrier height（BH）remains constant around 0.57 V.The Norde calculation technique gives a similar BH value of 0.69 V but the series resistance reaches higher values of 5500Ω.The indium doping level influences on the characteristics of Ag/SnO2：In/Si/Au MOS diode while the 4% indium level causes the capacitance inversion and the device turns into p-type material.

Percolation effects in the capacitive properties of metal-oxide varistors in the range of high voltage

C-V characteristics of ZnO-based ceramic structures used in manufacturing high-voltage and low-voltage varistors of different chemical compositions and manufacturing techniques have been investigated.A correlation between the intensity of electric field corresponding to transition of the C-V characteristics to the negative capacitances and average sizes of grains of a varistor structure has been established.Obtained data have been interpreted with the use of notions of the percolation theory of electric conductivity.The Shklovskii-De Gennes model has been used.It has been shown that on the highly nonlinear segment of C-V characteristics of a varistor structure,the size of an infinite cluster are limited to several intercrystallite potential barriers.This result is observed in all kinds of investigated varistor ceramics.