Neural Network and Fuzzy Control Based 11-Level Cascaded Inverter Operation

This paper presents a combined control and modulation technique to enhance the power quality(PQ)and power reliability(PR)of a hybrid energy system(HES)through a single-phase 11-level cascaded H-bridge inverter(11-CHBI).The controller and inverter specifically regulate the HES and meet the load demand.To track optimum power,a Modified Perturb and Observe(MP&O)technique is used for HES.Ultra-capacitor(UCAP)based energy storage device and a novel current control strategy are proposed to provide additional active power support during both voltage sag and swell conditions.For an improved PQ and PR,a two-way current control strategy such as the main controller(MC)and auxiliary controller(AC)is suggested for the 11-CHBI operation.MC is used to regulate the active current component through the fuzzy controller(FC),and AC is used to regulate the dc-link voltage of CHBI through a neural network-based PI controller(ANN-PI).By tracking the reference signals fromMC and AC,a novel hybrid pulse widthmodulation(HPWM)technique is proposed for the 11-CHBI operation.To justify and analyze the MATLAB/Simulink software-based designed model,the robust controller performance is tested through numerous steady-state and dynamic state case studies.

Model Predictive Control for Cascaded H-Bridge PV Inverter with Capacitor Voltage Balance

We designed an improved direct-current capacitor voltage balancing control model predictive control(MPC)for single-phase cascaded H-bridge multilevel photovoltaic(PV)inverters.Compared with conventional voltage balanc-ing control methods,the method proposed could make the PV strings of each submodule operate at their maximum power point by independent capacitor voltage control.Besides,the predicted and reference value of the grid-connected current was obtained according to the maximum power output of the maximum power point tracking.A cost function was con-structed to achieve the high-precision grid-connected control of the CHB inverter.Finally,the effectiveness of the proposed control method was verified through a semi-physical simulation platform with three submodules.

Intensification of Power Quality Using PMSG and Cascaded Multi Cell Trans-Z-Source Inverter

This script depicts the power quality intensification of Wind Energy Transfer System (WETS) using Permanent Magnet Synchronous Generator (PMSG) and Cascaded Multi Cell Trans-Z-Source Inverter (CMCTZSI). The PMSG knocks the induction generator and earlier generators, because of their stimulating performances without taking the frame power. The Trans-Z-Source Inverter with one transformer and one capacitor is connected newly. To increase the boosting ratio gratuity a cascaded impression is proposed with adopting multi-winding transformer which provides an option for this manuscript to use coupled inductor as an alternative of multi-winding transformer and remains the matching voltage gain as cascaded multi cell trans-Z- source inverter. Accordingly the parallel capacitances are also balancing the voltage gain. The parallel correlation of the method is essentially to trim down the voltage stresses and to improve the input current gain of the inverter. By using MALAB Simulation, harmonics can be reduced up to 1.32% and also DC side can be boosted up our required level 200 - 1000 V achievable. The new hardware setup results demonstrate to facilitate the multi cell Trans Z-source inverter. This can be generated high-voltage gain [50 V - 1000 V] and also be credible. Moreover, the level of currents, voltages and Harmonics on the machinery is low.

Modeling and Analysis of Variable Frequency Inverted Sine PWM Technique for a Hybrid Cascaded Multilevel Inverter

In cascaded H-bridge multilevel inverter, a variable frequency inverted sine PWM technique is modeled for hybrid electric vehicles. It has a particular advantage of increasing power which is achieved using series connection of H-bridge and also this topology is capable to produce superior spectral quality with considerable improvement of fundamental voltage. The variable frequency inverted sine PWM technique produces lesser torque ripple and enhances the fundamental output voltage mainly at lower modulation index ranges. The topologies of multilevel inverter are flying capacitor, diode clamped and cascaded inverter. In the paper, we will discuss about the cascaded multilevel inverter based on inverted sine PWM technique. The two switching strategies widely used to control multilevel inverters are constant frequency inverted sine PWM (CF-ISPWM) and variable frequency inverted sine PWM (VF-ISPWM). This implies that switch utilization substantially reduces 32.35% of the constant frequency inverted sine PWM switching technique. The performance of the technique is validated in terms of Total Harmonic Distortion (THD) and Torque ripple which significantly reduces when compared to constant frequency ISPWM. The analysis of conventional triangular PWM inverter and inverted sine PWM inverter using constant and variable switching scheme is done in MATLAB Simulink and verified experimentally by FPGA Spartan 3E processor.

A Cascade Multilevel Inverter Using a Single DC Source

3.SWITCHING ANGLES If the nominal capacitor voltage is chosen as Vdc/2, then one can compute the switching anglesθ1,θ2,andθ3.Following the development,the Fourier series expan- sion of the(staircase)output voltage waveform of the multilevel inverter as shown in Fig.2(a)

A Novel Multilevel Inverter Circuit for the Performance Enhancement of Direct Torque Controlled Induction Motor

Induction motor is the most sought after motor in the industry for excellent performance characteristics and robustness. Developments in the Power Electronic circuitry have revolutionised the induction motor industry leading to the developments in various control strategies and circuits for motor control. Direct Torque Control (DTC) is one of the excellent control strategies preferred by industries for controlling the torque and flux in an induction machine. The main drawback of DTC is the presence of torque ripple which is slightly more than the acceptable limit. There are various parameters that introduce ripples in the electromagnetic torque, one of them being the type of inverter circuit. There are various types of inverter circuits available and the effect of each of them in the production of torque ripple is different. This work is an attempt to identify the influence of various multilevel inverter circuits on the torque ripple level and to propose the best inverter circuit. The influence of multilevel diode clamped inverter and cascaded H bridge inverter circuits on torque ripple minimization, is analysed using simulation studies for identifying the most suitable multilevel inverter circuit which gives minimum torque ripple. The results obtained from the simulation studies are validated by hardware implementation on 0.75 kW induction motor.

Performance Metric of Z Source CHB Multilevel Inverter FED IM for Selective Harmonic Elimination and THD Reduction

This paper focuses on a Z source cascaded multilevel inverter which is designed to minimize harmonics in the output voltage. A balanced dc-link peak voltage can be achieved. The power generation module is built by PV panels which are connected to Z-Source Cascade H-bridge inverter. Cascaded multilevel inverter can achieve the distributed maximum power point tracking to increase the system efficiency and achieve high voltage/high power grid tie without a transformer. This paper analyzes the different PWM switching scheme and the operating states of a ZSI module and comparison is made with different PWM and total harmonic distortion of various PWM schemes.

Reduction of THD in Thirteen-Level Hybrid PV Inverter with Less Number of Switches

Multilevel inverter (MLI) is one of the most efficient power converters which are especially suited for high power applications with reduced harmonics. MLI not only achieves high output power and is also used in renewable energy sources such as photovoltaic, wind and fuel cells. Among various topologies of MLI, this paper mainly focuses on cascaded MLI with three unequal DC sources called asymmetric cascaded MLI which reduces the number of power switches. Various modulation techniques are also reviewed in literature [1]. In this paper we focus on sinusoidal (or) multicarrier pulse width modulation (SPWM) which improves the output voltage at lower modulation index for obtaining lower Total Harmonic Distortion (THD) level. The gating signal for the 13-level hybrid inverter using SPWM technique is generated using Field Programmable Gate Array (FPGA) processor. The proposed modulation technique results in reduced percentage of THD, but lower order harmonics are not eliminated. So a new technique called Selective Harmonic Elimination (SHE) is also implemented in order to reduce the lower order harmonics. The optimum switching angles are determined for obtaining minimum THD. The performance evaluation of the proposed PWM inverter is verified using an experimental model of 13-level cascaded hybrid MLI and compared with MATLAB/SIMULINK model.

Evaluation of 1.2 kV SiC MOSFETs in Multilevel Cascaded H-bridge Three-phase Inverter for Medium-voltage Grid Applications

A study is conducted to evaluate 1.2 kV silicon-carbide(SiC)MOSFETs in a cascaded H-bridge(CHB)three-phase inverter for medium-voltage applications.The main purpose of this topology is to remove the need for a bulky 60 Hz transformer normally used to step up the output signal of a voltage source inverter to a medium-voltage level.Using SiC devices(1.2-6.5 kV SiC MOSFETs)which have a high breakdown voltage,enables the system to meet and withstand the medium-voltage stress using only a minimal number of cascaded modules.The SiC-based power electronics when used in the presented topology considerably reduce the complexity usually encountered when Si devices are used to meet the medium-voltage level and power scalability.Simulation and preliminary experimental results on a low-voltage prototype verifies the nine-level CHB topology presented in this study.

A low-power DCO using inverter interlaced cascaded delay cell

This paper presents a low-power small-area digitally controlled oscillator （DCO） using an inverters interlaced cascaded delay cell （IICDC）. It uses a coarse-fine architecture with binary-weighted delay stages for the delay range and resolution. The coarse-tuning stage of the DCO uses IICDC, which is power and area efficient with low phase noise, as compared with conventional delay cells. The ADPLL with a DCO is fabricated in the UMC 180-nm CMOS process with an active area of 0.071 mm2. The output frequency range is 140-600 MHz at the power supply of 1.8 V. The power consumption is 2.34 mW@ a 200 MHz output.