为了减小氮化镓驱动电路高频工作时的损耗,针对共栅共源氮化镓高电子迁移率晶体管(Cascode GaN HEMT)提出一种高频谐振驱动电路,采用储能元件替代传统驱动电路中的耗能元件,电感电流为GaN器件栅极电容充/放电,有源密勒钳位电路抑制桥臂...为了减小氮化镓驱动电路高频工作时的损耗,针对共栅共源氮化镓高电子迁移率晶体管(Cascode GaN HEMT)提出一种高频谐振驱动电路,采用储能元件替代传统驱动电路中的耗能元件,电感电流为GaN器件栅极电容充/放电,有源密勒钳位电路抑制桥臂串扰。该文重点研究高频谐振驱动电路的工作模态,对电路损耗进行详细分析,给出电感取值的选取原则,并利用PSIM软件对电路进行仿真。最终搭建实验平台对电路的性能进行测试。结果表明,电感为电容充/放电提供低阻抗通路,能有效减小GaN器件驱动电路的电压振荡,明显降低驱动电路的损耗。仿真和实验同时证明了所提出的电路具有较好的性能。展开更多
A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteri...A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteristic test shows that the output i dB compression point is about -8.5 dBm at 334 GHz and the maximum efficiency is obtained at the point, which is slightly below the 1 dB compression point. Compared with the conventional hybrid integrated circuit, a major advantage of the monolithic integrated circuit is the significant improvement of reliability and consistency. In this work, a terahertz monolithic frequency multiplier at this band is designed and fabricated.展开更多
Efficient light generation and amplification has long been missing on the silicon platform due to its well-known indirect bandgap nature.Driven by the size,weight,power and cost(SWaP-C)requirements,the desire to fully...Efficient light generation and amplification has long been missing on the silicon platform due to its well-known indirect bandgap nature.Driven by the size,weight,power and cost(SWaP-C)requirements,the desire to fully realize integrated silicon electronic and photonic integrated circuits has greatly pushed the effort of realizing high performance on-chip lasers and amplifiers moving forward.Several approaches have been proposed and demonstrated to address this issue.In this paper,a brief overview of recent progress of the high-performance lasers and amplifiers on Si based on different technology is presented.Representative device demonstrations,including ultra-narrow linewidthⅢ-Ⅴ/Si lasers,fully integratedⅢ-Ⅴ/Si/Si3N4 lasers,high-channel count mode locked quantum dot(QD)lasers,and high gain QD amplifiers will be covered.展开更多
At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed i...At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.展开更多
The folded-cascode structure is used to realize the low-voltage low-power consumption mixer, whose performance parameters have big influence on the navigation radio receiver＇s performance. Adopting the folded-cascode...The folded-cascode structure is used to realize the low-voltage low-power consumption mixer, whose performance parameters have big influence on the navigation radio receiver＇s performance. Adopting the folded-cascode structure, the folded-cascode mixer （FCM） has a lower power supply voltage of 1.2 V and realizes the design trade-offs among the high transconductance, high linearity and low noise. The difficulties of realizing the trade-offs between the linearity and noise performance, the linearity and conversion gain, the conversion gain and noise performance are reduced. Fabricated in an radio frequency （RF） 0.18 μm CMOS process, the FCM has an active area of about 200 μm ×150 μm and consumes approximate 3.9 mW. The test results show that the FCM features a conversion gain （Gc） of some 14.5 dB, an input 1 dB compression point （Pin-1dB） of almost -13 dBm and a dual sideband （DSB） noise figure of around 12 dB. The FCM can be applied to the navigation radio receivers and electronic systems for aviation and aerospace or other related fields.展开更多
介绍了一种超低功耗、无片上电阻、无双极型晶体管（BJT）的基于亚阈值CMOS特性的基准电压源,该带隙基准源主要用于低功耗型专用集成电路（ASIC）。采用Oguey电流源结构来减小静态电流,以降低功耗。通过使用工作在线性区的MOS管代替传...介绍了一种超低功耗、无片上电阻、无双极型晶体管（BJT）的基于亚阈值CMOS特性的基准电压源,该带隙基准源主要用于低功耗型专用集成电路（ASIC）。采用Oguey电流源结构来减小静态电流,以降低功耗。通过使用工作在线性区的MOS管代替传统结构中的电阻消除迁移率和电流的温度影响,同时减小芯片面积;采用共源共栅电流镜以降低电源电压抑制比和电压调整率。电路基于SMIC 0.18μm CMOS工艺进行仿真。仿真结果表明,在-45~130℃内,温漂系数为29.1×10-6/℃,电源电压范围为0.8~3.3 V时,电压调整率为0.056%,在100 Hz时,电源电压抑制比为-53 d B。电路功耗仅为235 n W,芯片面积为0.01 mm2。展开更多
文摘为了减小氮化镓驱动电路高频工作时的损耗,针对共栅共源氮化镓高电子迁移率晶体管(Cascode GaN HEMT)提出一种高频谐振驱动电路,采用储能元件替代传统驱动电路中的耗能元件,电感电流为GaN器件栅极电容充/放电,有源密勒钳位电路抑制桥臂串扰。该文重点研究高频谐振驱动电路的工作模态,对电路损耗进行详细分析,给出电感取值的选取原则,并利用PSIM软件对电路进行仿真。最终搭建实验平台对电路的性能进行测试。结果表明,电感为电容充/放电提供低阻抗通路,能有效减小GaN器件驱动电路的电压振荡,明显降低驱动电路的损耗。仿真和实验同时证明了所提出的电路具有较好的性能。
基金Supported by the National High-Technology Research and Development Program of China under Grant No 2011AA010203the National Basic Research Program of China under Grant Nos 2011CB201704 and 2010CB327502the National Natural Science Foundation of China under Grant Nos 61434006 and 61106074
文摘A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteristic test shows that the output i dB compression point is about -8.5 dBm at 334 GHz and the maximum efficiency is obtained at the point, which is slightly below the 1 dB compression point. Compared with the conventional hybrid integrated circuit, a major advantage of the monolithic integrated circuit is the significant improvement of reliability and consistency. In this work, a terahertz monolithic frequency multiplier at this band is designed and fabricated.
文摘Efficient light generation and amplification has long been missing on the silicon platform due to its well-known indirect bandgap nature.Driven by the size,weight,power and cost(SWaP-C)requirements,the desire to fully realize integrated silicon electronic and photonic integrated circuits has greatly pushed the effort of realizing high performance on-chip lasers and amplifiers moving forward.Several approaches have been proposed and demonstrated to address this issue.In this paper,a brief overview of recent progress of the high-performance lasers and amplifiers on Si based on different technology is presented.Representative device demonstrations,including ultra-narrow linewidthⅢ-Ⅴ/Si lasers,fully integratedⅢ-Ⅴ/Si/Si3N4 lasers,high-channel count mode locked quantum dot(QD)lasers,and high gain QD amplifiers will be covered.
文摘At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.
文摘The folded-cascode structure is used to realize the low-voltage low-power consumption mixer, whose performance parameters have big influence on the navigation radio receiver＇s performance. Adopting the folded-cascode structure, the folded-cascode mixer （FCM） has a lower power supply voltage of 1.2 V and realizes the design trade-offs among the high transconductance, high linearity and low noise. The difficulties of realizing the trade-offs between the linearity and noise performance, the linearity and conversion gain, the conversion gain and noise performance are reduced. Fabricated in an radio frequency （RF） 0.18 μm CMOS process, the FCM has an active area of about 200 μm ×150 μm and consumes approximate 3.9 mW. The test results show that the FCM features a conversion gain （Gc） of some 14.5 dB, an input 1 dB compression point （Pin-1dB） of almost -13 dBm and a dual sideband （DSB） noise figure of around 12 dB. The FCM can be applied to the navigation radio receivers and electronic systems for aviation and aerospace or other related fields.
文摘介绍了一种超低功耗、无片上电阻、无双极型晶体管（BJT）的基于亚阈值CMOS特性的基准电压源,该带隙基准源主要用于低功耗型专用集成电路（ASIC）。采用Oguey电流源结构来减小静态电流,以降低功耗。通过使用工作在线性区的MOS管代替传统结构中的电阻消除迁移率和电流的温度影响,同时减小芯片面积;采用共源共栅电流镜以降低电源电压抑制比和电压调整率。电路基于SMIC 0.18μm CMOS工艺进行仿真。仿真结果表明,在-45~130℃内,温漂系数为29.1×10-6/℃,电源电压范围为0.8~3.3 V时,电压调整率为0.056%,在100 Hz时,电源电压抑制比为-53 d B。电路功耗仅为235 n W,芯片面积为0.01 mm2。
