An NMOS output-capacitorless low-dropout regulator with dynamic-strength event-driven charge pump

In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.

Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

Self-Balanced Charge Pump with Fast Lock Circuit

A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.

Design and noise analysis of a fully-differential charge pump for phase-locked loops

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.

A multi-mode low ripple charge pump with active regulation

In order to improve efficiency and reduce the output ripple, a novel multi-mode charge pump is presented. The proposed charge pump includes dual-loop regulation topology-skip and linear modes. It consumes low quiescent current in skip mode for light loads, and produces low ripple in linear mode for heavy loads, which closes the gap between linear mode and skip mode with active regulation; a multi-mode charge pump employing the technique has been implemented in the UMC 0.6-μm-BCD process. The results indicate that the charge pump works well and effectively; it has low ripple with special regulation, and minimizes the size of the capacitance, then decreases the area of the PCB board. The adjustable output of the positive charge pump is 10-30 V, and the maximum output ripple is 100 mV when the load current is 200 mA. The line regulation is 0.2%/V, and load regulation is 0.075%.

Research and design of a novel current mode charge pump

To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier.In the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage ripple.The charge pump small-signal model is used to describe the device’s dynamic behavior and stability.Analytical predictions were verified by Hspice simulation and testing.Load driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 mV.The output response time is less than 8μs,and the load current jumps from 400 to 800 mA.

A novel low ripple charge pump with a 2X/1.5X booster for PCM

A low ripple switched capacitor charge pump applicable to phase change memory （PCM） is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo- 14n during the charge phase （Vo is the prospective output voltage）. In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.

Charge Pump for LCD Driver Used in Cell Phone

A charge pump design is presented to operate at 10 kHz with 100 μA in a liquid crystal display (LCD) driver for cell phone. Optimal channel widths are designed by estimating the power consumption of the Fibonacci-like charge pump. An optimal frequency is a compromise between the rise time and the dynamic power dissipation. The optimization of the two-phase nonoverlapping clock generator circuit improves the efficiency. Simulation results based on 1.2 μm complementary metal-oxide-semiconductor (CMOS) technology parameters verify the efficiency of the design.

An area-saving and high power efficiency charge pump built in a TFT-LCD driver IC

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC-DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump＇s power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter （BPF） with on chip charge pump auto-tuning is presented. It is implemented in UMC （United Manufacturing Corporation） 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point （ⅡP3） is 16.621 dBm, with 50Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS （global positioning system） and Bluetooth systems.

Diagram representations of charge pumping processes in CMOS transistors

A diagram representation method is proposed to interpret the complicated charge pumping（CP） processes. The fast and slow traps in CP measurement are defined.Some phenomena such as CP pulse rise/fall time dependence, frequency dependence,the voltage dependence for the fast and slow traps,and the geometric CP component are clearly illustrated at a glance by the diagram representation.For the slow trap CP measurement,there is a transition stage and a steady stage due to the asymmetry of the electron and hole capture,and the CP current is determined by the lower capturing electron or hole component.The method is used to discuss the legitimacy of the newly developed modified charge pumping method.

A dual mode charge pump with adaptive output used in a class G audio power amplifier

A dual mode charge pump to produce an adaptive power supply for a class G audio power amplifier is presented.According to the amplitude of the input signals,the charge pump has two level output voltage rails available to save power.It operates both in current mode at high output load and in pulse frequency modulation （PFM） at light load to reduce the power dissipation.Also,dynamic adjustment of the power stage transistor size based on load current at the PFM mode is introduced to reduce the output voltage ripple and prevent the switching frequency from audio range.The prototype is implemented in 0.18μm 3.3 V CMOS technology.Experimental results show that the maximum power efficiency of the charge pump is 79.5%@ 0.5x mode and 83.6%@ lx mode.The output voltage ripple is less than 15 mV while providing 120 mA of the load current at PFM control and less than 18 mV while providing 300 mA of the load current at current mode control.An analytical model for ripple voltage and efficiency calculation of the proposed PFM control demonstrates reasonable agreement with measured results.

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop （PLL） characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector （PFD） to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

A novel charge pump drive circuit for power MOSFETs

Novel improved power metal oxide semiconductor field effect transistor （MOSFET） drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

A CMOS AC/DC charge pump for a wireless sensor network

An AC/DC charge pump implemented with MOS FETs has been presented for wireless sensor network applications.The proposed AC/DC charge pump can generate a stable output with low power dissipation and high pumping efficiency,which has been implemented in 0.13μm CMOS technology.The proposed charge pump employs MOSFET diodes with low thresholds,and improves the conversion efficiency.The analytical model of the voltage multiplier,the simulation results,and the chip testing results are presented.

Analysis of switch-induced error voltage for automatic conversion mode change charge pumps

This paper presents an exact expression for switch-induced error voltage which would cause a spike voltage on the output capacitor of the automatic conversion mode change （ACMC） charge pumps. The spike voltage will introduce several undesired problems--large output voltage ripple, serious frequency noise and low efficiency. Some methods used for reducing the spike voltage are provided by the proposed expression. An equivalent lumped model is used for deducing the expression. The ACMC charge pump circuit has been designed in SILTERRA 0.18/xm CMOS process. The experiment results show that the value of the spike voltage can match the expression well. Compared with three different improved versions, the spike voltage caused by the switch-induced error voltage can be reduced obviously.

A high-efficiency charge pump in BCD process for implantable medical devices

This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS（BCD） technology for implantable medical devices.Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm^2.

A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse

A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .