Performance of beam-type piezoelectric vibration energy harvester based on ZnO film fabrication and improved energy harvesting circuit

We demonstrate a piezoelectric vibration energy harvester with the ZnO piezoelectric film and an improved synchronous electric charge extraction energy harvesting circuit on the basis of the beam-type mechanical structure,especially investigate its output performance in vibration harvesting and ability to generate charges.By establishing the theoretical model for each of vibration and circuit,the numerical results of voltage and power output are obtained.By fabricating the prototype of this harvester,the quality of the sputtered film is explored.Theoretical and experimental analyses are conducted in open-circuit and closed-circuit conditions,where the open-circuit mode refers to the voltage output in relation to the ZnO film and external excitation,and the power output of the closed-circuit mode is relevant to resistance.Experimental findings show good agreement with the theoretical ones,in the output tendency.It is observed that the properties of ZnO film achieve regularly direct proportion to output performance under different excitations.Furthermore,a maximum experimental power output of 4.5 mW in a resistance range of 3 kΩ-8 kΩis achieved by using an improved synchronous electric charge extraction circuit.The result is not only more than three times the power output of classic circuit,but also can broaden the resistance to a large range of 5 kΩunder an identical maximum value of power output.In this study we demonstrate the fundamental mechanism of piezoelectric materials under multiple conditions and take an example to show the methods of fabricating and testing the ZnO film.Furthermore,it may contribute to a novel energy harvesting circuit with high output performance.

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.

A 27-mW 10-bit 125-MSPS charge domain pipelined ADC with a PVT insensitive boosted charge transfer circuit

A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.

A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit

A low power 10-bit 250 MSPS charge-domain （CD） pipelined analog-to-digital converter （ADC） is introduced. The ADC is implemented in MOS bucket-brigade devices （BBDs） based CD pipelined architecture. A replica controlled boosted charge transfer （BCT） circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. The ADC achieves an SFDR of 64.4 dB, an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is ＋0.5/- 0.55 LSB and INL is ＋0.8/- 0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.

Charge Pump for LCD Driver Used in Cell Phone

A charge pump design is presented to operate at 10 kHz with 100 μA in a liquid crystal display (LCD) driver for cell phone. Optimal channel widths are designed by estimating the power consumption of the Fibonacci-like charge pump. An optimal frequency is a compromise between the rise time and the dynamic power dissipation. The optimization of the two-phase nonoverlapping clock generator circuit improves the efficiency. Simulation results based on 1.2 μm complementary metal-oxide-semiconductor (CMOS) technology parameters verify the efficiency of the design.

High voltage generator circuit with low power and high efficiency applied in EEPROM

This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory（EEPROM）.The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique.The high efficiency is dependent on the zero threshold voltage（V_（th）） MOSFET and the charge transfer switch（CTS） charge pump.The proposed high voltage generator circuit has been implemented in a 0.35μm EEPROM CMOS process.Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48μW and a higher pumping efficiency（83.3%） than previously reported circuits.This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pellieoni structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.