In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loo...In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.展开更多
This paper proposes a repeater for boosting the speed of interconnects with low power dissipation.We have designed and implemented at 45 and 32 nm technology nodes.Delay and power dissipation performances are analyzed...This paper proposes a repeater for boosting the speed of interconnects with low power dissipation.We have designed and implemented at 45 and 32 nm technology nodes.Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations.A significant reduction in delay and power dissipation are observed compared to a conventional repeater.The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance.The proposed repeater is also compared with LPTG CMOS repeater,and the results shows that the proposed repeater has reduced delay.The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.展开更多
A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with r...A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with reduced current mismatch.VCOs that determine the out-band phase noise of a phase-locked loop(PLL)based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor.A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors.Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs.Fabricated in a TSMC 0.18-μm CMOS process,the prototype operates from 0.20 to 2.43 GHz.The PLL synthesizer achieves an in-band phase noise of-96.8 dBc/Hz and an out-band phase noise of-122.8 dBc/Hz at the 2.43-GHz carrier.The root-mean-square jitter is 1.2 ps under the worst case,and the measured reference spurs are less than-65.3 dBc.The current consumption is 15.2 mA and the die occupies 850μm×920μm.展开更多
基金supported by the National Natural Science Foundation of China under Grant 62274189the Natural Science Foundation of Guangdong Province,China,under Grant 2022A1515011054the Key Area R&D Program of Guangdong Province under Grant 2022B0701180001.
文摘In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.
文摘This paper proposes a repeater for boosting the speed of interconnects with low power dissipation.We have designed and implemented at 45 and 32 nm technology nodes.Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations.A significant reduction in delay and power dissipation are observed compared to a conventional repeater.The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance.The proposed repeater is also compared with LPTG CMOS repeater,and the results shows that the proposed repeater has reduced delay.The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.
基金Project supported by the National Natural Science Foundation of China(No.61376031)。
文摘A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with reduced current mismatch.VCOs that determine the out-band phase noise of a phase-locked loop(PLL)based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor.A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors.Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs.Fabricated in a TSMC 0.18-μm CMOS process,the prototype operates from 0.20 to 2.43 GHz.The PLL synthesizer achieves an in-band phase noise of-96.8 dBc/Hz and an out-band phase noise of-122.8 dBc/Hz at the 2.43-GHz carrier.The root-mean-square jitter is 1.2 ps under the worst case,and the measured reference spurs are less than-65.3 dBc.The current consumption is 15.2 mA and the die occupies 850μm×920μm.
