Planar ion chip design for scalable quantum information processing

We investigate a planar ion chip design with a two-dimensional array of linear ion traps for scalable quantum information processing. Qubits are formed from the internal electronic states of trapped ^40Ca^＋ ions. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate separately, a combination of appropriate rf and DC potentials is applied to them for stable ion confinement. Every two adjacent electrodes can generate a linear ion trap in and between the electrodes above the chip at a distance dependent on the geometrical scale and other considerations. The potential distributions are calculated by using a static electric field qualitatively. This architecture provides a conceptually simple avenue to achieving the microfabrication and large-scale quantum computation based on the arrays of trapped ions.

Lathe process of AZ91D magnesium alloy chips used in semi-solid thixomolding

Based on the mechanism of chip breaking and the principle of semi-solid thixomolding, the lathe process of AZ91D magnesium alloys chips used in semi-solid thixotropic injection molding process was studied. With three kinds of turning tools, such as 31303C5, 31003C and 31303C, different chips were gotten. And by one tool with different lathe parameters, different chips were gotten. The results show that, under the needed condition of the thixotropic injection molding machine, the ideal chips are gotten and the size of magnesium alloy chips must be about 35mm, and the turning tool is chosen, whose chip breaker groove is narrower and the depth of cutting is more than 3mm as well as the amount of feed is larger than 0.3mm. The deformation occurs on the microstructure of the chips, and the residual stress is important to the later microstructure of semi-solid state in injection molding.

ANALYSIS AND DESIGN OF A NEURAL CHIP USED FOR BINARY IMAGE PROCESSING

Based on the model of a formal neuron proposed by McCulloch and Pitts,a kind ofneural circuit,which is a CMOS Variable Threshold Logic(VTL)circuit,is given in this paperconsidering the features of the binary image processing system.The theoretical analysis,andthe simulations for the building block circuits such as D/A converters,comparator and so on aregiven.The layout design of the whole circuit are also given.The binary image processing can berealized by using the VTL circuit combined with its external auxiliary circuits.

DS/SS系统中Chip波形对系统抗单频干扰能力的影响

随着 DS/SS系统的广泛应用 ,提高系统抗干扰能力一直是扩频通信研究的热点之一。扩频系统的处理增益作为衡量系统抗干扰能力的主要指标 ,通常等于单位数据比特内 Chip的个数 N。当系统受到强干扰时 ,系统的抗干扰性能会下降。首先分析了 DS/SS系统的抗单频干扰能力 ,然后讨论了系统 Chip波形对处理增益的影响 ,最后指出了系统 Chip波形的幅度谱在零点处取值较小时可以获得大的系统处理增益。

下一代测序中ChIP-seq数据的处理与分析

将染色质免疫共沉淀技术(ChIP)与下一代高通量测序技术相结合的染色质免疫共沉淀测序(ChIP-seq),已成为功能基因组学、特别是基因表达调控领域研究的关键技术。ChIP-seq实验带来的海量数据向生物信息学研究人员提出了新的挑战。由于此领域数据处理技术的发展大大滞后于实验技术进步,有必要系统地介绍和回顾ChIP-seq数据处理的各个方面,以便更多研究人员进入此领域设计或改进相应的算法。文章结合实例详细介绍了ChIP-seq数据整个流程,并重点讨论了其中的主要问题和关键环节,为这一研究领域的科研人员提供一个快速而深入的认识。

基于Arduino与Processing互动编程的特种仓库智能测控系统设计

基于Arduino与Processing互动编程方式进行特种仓库智能测控系统设计。该系统以Arduino为主控单元,利用各种传感器实时采集库区火情、烟雾、温度、湿度、有害气体浓度等关键参数;采用中位值平均滤波法对参数进行处理,并根据库内参数发出相应控制信号,作用于对应节点设备,实现自动控制。同时,保留人工干预措施,仓库管理人员可以根据库内环境参数做出相应的管控措施。所设计系统是集常规监测、自动控制、无人值班等功能于一体的智能化系统,对弹药、危险品、生化物品等高危物品的存储有一定的借鉴意义。

Adiabatic Shear Mechanisms for the Hard Cutting Process

The most important consequence of adiabatic shear phenomenon is formation of sawtooth chip. Lots of scholars focused on the formation mechanism of sawtooth, and the research often depended on experimental approach. For the present, the mechanism of sawtooth chip formation still remains some ambiguous aspects. This study develops a combined numerical and experimental approach to get deeper understanding of sawtooth chip formation mechanism for Polycrystalline Cubic Boron Nitride（PCBN） tools orthogonal cutting hard steel GCr15. By adopting the Johnson-Cook material constitutive equations, the FEM simulation model established in this research effectively overcomes serious element distortions and cell singularity in high strain domain caused by large material deformation, and the adiabatic shear phenomenon is simulated successfully. Both the formation mechanism and process of sawtooth are simulated. Also, the change features regarding the cutting force as well as its effects on temperature are studied. More specifically, the contact of sawtooth formation frequency with cutting force fluctuation frequency is established. The cutting force and effect of cutting temperature on mechanism of adiabatic shear are investigated. Furthermore, the effects of the cutting condition on sawtooth chip formation are researched. The researching results show that cutting feed has the most important effect on sawtooth chip formation compared with cutting depth and speed. This research contributes a better understanding of mechanism, feature of chip formation in hard turning process, and supplies theoretical basis for the optimization of hard cutting process parameters.

Random testing for system-level functional verification of system-on-chip

In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.

Signal processing for PSoC based PIR motion detection

A signal processing scheme for a programmable system-on-chip(PSoC)based human body infrared tracking system is described.The purpose of this project is to convert the analog signal from a passive infrared(PIR)sensor to a digital signal which will be used to calculate the correct position of a human body.This paper covers the analog design with PSoC,the analog to digital conversion and the software to eliminate noise.

CHIP 2021评测任务1概述:医学对话临床发现阴阳性判别任务

介绍基于医学对话的信息抽取相关研究现状,结合第七届中国健康信息处理会议组织的基于医学对话的临床发现阴阳性判别评测任务,阐述该任务评测数据集、评估指标,对比介绍前4名参赛者的方法并进行总结,以推进医疗人工智能领域的发展。

低温真空油炸柿子脆片工艺优化及其品质分析

本文以柿子为原料,开展油炸温度、油炸时间、脱油时间以及切片厚度4个单因素对低温真空油炸柿子品质影响,并根据Box-Behnken试验原理,以柿子脆片的脆度、色差为响应值对低温真空油炸柿子脆片加工工艺进行优化,进一步对最终产品理化成分、微生物指标和微观结构进行分析。结果表明,油炸温度、油炸时间、脱油时间和切片厚度都影响柿子脆片的脆度和色差,经响应面优化试验分析并根据实际修正确定低温真空油炸柿子脆片的最佳工艺为:脱油时间5 min、油炸时间50 min、油炸温度80℃、切片厚度5.5 mm。该条件下柿子脆片脆度858.97 g、色差值ΔE 17.28、水分含量2.60%、含油率为22.53%、可滴定酸0.34 g/L、V_(C)含量31.20 mg/100 g;柿子脆片产品色泽金黄、形状完整,脆片内部呈现蜂窝状多孔疏松结构,产品口感酥脆,微生物指标符合卫生要求。本研究可为柿子低温真空油炸脆片产品的开发提供技术支撑。

Design of Efficient Router with Low Power and Low Latency for Network on Chip

The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.

大蒜加工废水处理研究进展

我国是世界上最大的大蒜生产国和出口国,蒜片是主要的出口品种之一。每生产1 t蒜片会产生20 t以上的大蒜加工废水。大蒜加工废水具有强烈的杀菌作用,给其生物法处理带来了困难。文章围绕大蒜加工废水的特点和组成、大蒜素抑菌机理、大蒜加工废水的生物法处理、膜分离、高级氧化等工艺展开综述,以期为改进现有大蒜加工废水处理工艺提供借鉴。

Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips

A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.

ACF-COG芯片互连电阻建模与工艺参数优化

玻璃覆晶封装技术是液晶显示器生产过程中的核心技术,主要采用热固性固化胶和若干导电颗粒组成各向异性导电胶膜倒装实现互连,而互连后的芯片电阻是材料选择与工艺参数的重要评估指标。本文旨在建立芯片互连电阻仿真体系并探究相同导电颗粒分布下芯片封装的最优工艺参数。首先,通过大量实验获取采用CP6530ID型号各向异性导电胶膜的芯片在不同工艺参数下的凸点互连电阻及凸点捕捉到的导电颗粒数目,并对实验数据进行统计分析。其次,在数值模拟实验中,为模拟键合温度与压力的耦合方式,采用顺序热力耦合方法。在得到热力耦合场下CP6530ID型号各向异性导电胶膜中导电颗粒的形变量后,通过建立的导电颗粒互连电阻的数学模型算出芯片互连电阻,将互连电阻计算结果与实验结果对比,验证仿真结果的有效性及对实验的指导意义。最后,将生产商索尼化学公司推荐的封装工艺参数范围作为优化起点,对随机化导电颗粒分布情况进行仿真,以仿真结果为参考探究芯片封装的最优工艺参数。在实现芯片有效封装的前提下,仿真结果显示,键合温度为190℃、键合压力为100MPa时,芯片互连电阻最小。芯片封装过程中,压力对互连电阻起决定性作用,温度对互连电阻的影响较为微弱。就压力因子而言,在不考虑导电颗粒被压裂的情况下,压力越大,最后形成的互连电阻越小;温度越高,导电颗粒的热膨胀越剧烈,导致互连电阻越大。

基于STM32单片机的二维码门禁控制系统

该文介绍一种基于STM32单片机的二维码门禁控制系统。该系统通过集成图像采集、二维码识别、数据通信和控制逻辑等关键模块,实现高效、安全的门禁管理。首先,系统利用GM65图像传感器捕捉进出人员的二维码图像,然后通过STM32单片机的强大处理能力进行二维码解码,从而获取其中的身份信息。接着,系统将解码得到的数据与One-Net云端信息进行比对,以判断进出人员是否具有合法通行权限。若权限验证通过,则门禁设备执行开锁操作,允许人员通行;若验证不通过,则系统拒绝开锁,并记录相关事件。该系统的引入,不仅提升门禁管理的效率和安全性,还降低了人为操作的错误率,为智能化、自动化的门禁管理提供新的解决方案。

面向微流控芯片工作状态感知的智能泵:设计、实现和验证

针对微流控芯片内部流体状态实时预测和工作流程调控的需求,提出了一种基于“驱动器即传感器”理念的智能泵。对所提出智能泵系统工作原理和工作流程进行介绍,并对测试微流控芯片及工作状态预测需求进行分析。建立压力信号处理流程,气压信号经预处理后,提取有效时域特征,进行状态预测训练。进行微流控芯片工作状态验证,实验表明:智能泵预测磁珠球复溶结果和冻干球复溶结果与实际测量和生物实验结果相一致,验证了智能泵系统的有效性。

基于误差修正的激光扫描复杂零件加工系统

针对降低复杂零件加工过程中的零件误差问题,设计基于误差修正的激光扫描复杂零件加工系统。以激光扫描为基础设计复杂零件加工系统的整体架构。基于系统整体架构利用激光扫描模块获取材料信息,并采用网格修正法修正扫描单元中的振镜误差;将激光扫描结果传输至DSP控制模块内,通过直线、圆弧插补运算确定加工模块内不同加工单元的刀具加工路径,同时利用不同伺服单元的位置等反馈信号对比,实现机械手模块运动控制。实验结果显示该系统激光扫描误差控制在0.5 mm以下,符合风机应用标准,加工时间最高为37 min,有效提升了零件可应用率。

集成电路技术综述

集成电路技术是现代电子工程的核心技术之一,它推动了整个科技行业的发展。本文从集成电路的全产业链着手,从器件工艺、制造设备、设计工具和芯片门类4个角度出发,对国内和国际上集成电路技术和产业链的现状作了简要介绍。未来,随着技术的进步和应用需求的增长,集成电路仍将继续发挥重要作用,推动行业的持续发展。希望本文能够对国内的同行有所启发,丰富对于产业现状的认识和理解,为科研应用的方向和目标的确定提供一定的参考价值。

多种分辨率HDMI接口的TMDS信号转为LVDS格式实现方法研究

为了将图像仿真系统输出的高清多媒体接口(High Definition Multimedia Interface,HDMI)最小化传输差分信号(Transition Minimized Differential Signaling,TMDS)转换为摄像头模组接口低电压差分信号(Low-Voltage Differential Signaling,LVDS),文章联合使用ITE68051芯片和现场可编程逻辑门阵列芯片(Field Programmable Gate Array,FPGA)实现了相应的转换。首先,将高清、超高清HDMI接口的TMDS信号通过ITE68051视频处理芯片进行TMDS解码,以双端口方式输出并行RGB数字信号;然后,应用FPGA易编程性的特点,将多种分辨率的RGB信号转换为相应的LVDS信号。联合应用ITE68051和FPGA芯片架构的转换系统,便于视频设备之间的兼容和系统后续升级,为自动驾驶仿真系统的视频信号输入提供了可靠的硬件接口通道。