A 16bit sigma-delta audio analog-to-digital converter is developed.It consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the modulator.Chopper stabilizat...A 16bit sigma-delta audio analog-to-digital converter is developed.It consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the modulator.Chopper stabilization is applied to the first integrator to eliminate the 1/f noise.A low-power,area-efficient decimator is used,which includes a poly-phase comb-filter and a wave-digital-filter.The converter achieves a 92dB dynamic range over the 96kHz audio band.This single chip occupies 2.68mm2 in a 0.18μm six-metal CMOS process and dissipates only 15.5mW power.展开更多
A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch,a symmetrical readout circuit is realized.The linear input range is increased, an...A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch,a symmetrical readout circuit is realized.The linear input range is increased, and the systematic offsets of two input op-amps are cancelled.The common-mode noise and even-order distortion are also rejected.A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps,and a Verilog-A-based varactor is used to model the real variable sensing capacitor.Simulation results show that the output voltage of this proposed readout circuit responds correctly,while the under-test capacitance changes with a frequency of 1 kHz.A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF,linearity error below 1%and power consumption as low as 2.5 mW.This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.展开更多
文摘A 16bit sigma-delta audio analog-to-digital converter is developed.It consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the modulator.Chopper stabilization is applied to the first integrator to eliminate the 1/f noise.A low-power,area-efficient decimator is used,which includes a poly-phase comb-filter and a wave-digital-filter.The converter achieves a 92dB dynamic range over the 96kHz audio band.This single chip occupies 2.68mm2 in a 0.18μm six-metal CMOS process and dissipates only 15.5mW power.
文摘A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch,a symmetrical readout circuit is realized.The linear input range is increased, and the systematic offsets of two input op-amps are cancelled.The common-mode noise and even-order distortion are also rejected.A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps,and a Verilog-A-based varactor is used to model the real variable sensing capacitor.Simulation results show that the output voltage of this proposed readout circuit responds correctly,while the under-test capacitance changes with a frequency of 1 kHz.A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF,linearity error below 1%and power consumption as low as 2.5 mW.This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.
