Quantum algorithm for minimum dominating set problem with circuit design

Using quantum algorithms to solve various problems has attracted widespread attention with the development of quantum computing.Researchers are particularly interested in using the acceleration properties of quantum algorithms to solve NP-complete problems.This paper focuses on the well-known NP-complete problem of finding the minimum dominating set in undirected graphs.To expedite the search process,a quantum algorithm employing Grover’s search is proposed.However,a challenge arises from the unknown number of solutions for the minimum dominating set,rendering direct usage of original Grover’s search impossible.Thus,a swap test method is introduced to ascertain the number of iterations required.The oracle,diffusion operators,and swap test are designed with achievable quantum gates.The query complexity is O(1.414^(n))and the space complexity is O(n).To validate the proposed approach,qiskit software package is employed to simulate the quantum circuit,yielding the anticipated results.

A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

Trending IC design directions in 2022

For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially;and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit(IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence(AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

SOME COMBINATORIAL OPTIMIZATION PROBLEMS ARISING FROM VLSI CIRCUIT DESIGN

This paper is basically a survey to show a number of combinatorial optimization problems arising from VLSI circuit design. Some of them including the existence problem, minimax problem, net representation, bend minimization, area minimization, placement problem, routing problem, etc. are especially discussed with new results and theoretical ideas for treating them. Finally, a number of problems for further research are mentioned.

Design, Fabrication, and Modeling of CMOS-Compatible Double Photodiode

A double photodiode (PD) constructed by p+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-μm CMOS process. Based on the device structure and mechanism of double PD, a novel small-signal equivalent circuit model considering the carrier transit effect and the parasitic RC time constant was presented. By this model with complete electronic components, the double PD can be incorporated in a commercial circuit simulator. The component values were extracted by fitting the measured S-parameters using simulated annealing algorithm, and a good agreement between the measurement and the simulation results was achieved. © 2017, Tianjin University and Springer-Verlag Berlin Heidelberg.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

DESIGN OF TERNARY ADIABATIC MULTIPLIER ON SWITCH-LEVEL

The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be ob-tained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ter-nary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are charac-terized with distinctive low power consumption.

SIMULATION IN THERMAL DESIGN FOR ELECTRONIC CONTROL UNIT OF ELECTRONIC UNIT PUMP

The high working junction temperature of power component is the most common reason of its failure. So the thermal design is of vital importance in electronic control unit （ECU） design. By means of circuit simulation, the thermal design of ECU for electronic unit pump （EUP） fuel system is applied. The power dissipation model of each power component in the ECU is created and simulated. According to the analyses of simulation results, the factors which affect the power dissipation of components are analyzed. Then the ways for reducing the power dissipation of power components are carried out. The power dissipation of power components at different engine state is calculated and analyzed. The maximal power dissipation of each power component in all possible engine state is also carried out based on these simulations. A cooling system is designed based on these studies. The tests show that the maximum total power dissipation of ECU drops from 43.2 W to 33.84 W after these simulations and optimizations. These applications of simulations in thermal design of ECU can greatly increase the quality of the design, save the design cost and shorten design time

Applications of modularized circuit designs in a new hyper-chaotic system circuit implementation

Modularized circuit designs for chaotic systems are introduced in this paper.Especially,a typical improved modularized design strategy is proposed and applied to a new hyper-chaotic system circuit implementation.In this paper,the detailed design procedures are described.Multisim simulations and physical experiments are conducted,and the simulation results are compared with Matlab simulation results for different system parameter pairs.These results are consistent with each other and they verify the existence of the hyper-chaotic attractor for this new hyper-chaotic system.

DESIGN OF LIGHTWEIGHT PUF CIRCUIT BASED ON SELECTABLE CROSS-COUPLED INVERTERS

By analyzing the principle of process variations, a lightweight Physical Unclonable Function （PUF） circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation （SMIC） 65 nm CMOS technology and the layout area is 2.94μm × 1.68μm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.

Design and Implementation of a Photovoltaic Data Acquisition System for Some Meteorological Variables

In this paper we have developed a data logging and monitoring system, we validated the system by comparing the result from it with the existing one and found that the system performs slightly better than the existing work in the same area. This implies that the data logger and monitoring system is good and can be used to monitor solar energy variables even at the comfort of our homes. We fitted a model to the generated data and found that the meteorological variables considered accounted for 99.88% of the power output in the rainy seasons while 0.12% of the variation was not explained due to other factors. Solar panels inclined at an angle of 5° (Tilt) and facing South Pole perform optimally.

Design of Digital Circuit Experiment Course Based on FPGA

With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.

THE DESIGN OF HIGH PERFORMANCE LINEAR TRANSCONDUCTOR

An improved structure of linear transconductor is presented in this paper. It is analyzed in theory and simulated with Spectre based on 0.25μm CMOS process. The simulation results show that the differential input voltage of the proposed transconductor is 4.0Vpp(peak to peak), whereas the differential input voltage of the existing source degeneration structure is 2.2Vpp, when their nonlinear errors are required to be less than 0.15%.

Microwave Integrated Circuit Design Handbook

作者:Reinmut K.Hoffmann(1984 IEEE微波奖获得者) 出版:Artech House公司(美国)1987年本书给出适于微波工程师和研究人员应用的有关MIC方面的基础技术、电性能和设计。侧重于电性能分析和设计,强调应用。对于每一种设计技术和应用均作出较清楚的叙述和完整的处理。本书尽量给出电路的物理描述,避免过于冗长的数学公式,内容包含对下列议题的详细评述与研讨:

The Design of Circuit for Checking Short in HT-7U Superconducting Tokamak Device

The tokamak HT-7U project has been funded as a Chinese national project since 1998. The main object of the project is to build a nuclear fusion experimental device with divertor configuration, which is designed by the Institute of Plasma Physics, the Chinese Academy of Sciences (ASIPP). It is a full superconducting device, consisting of superconducting toroidal field (TF) coils and superconducting poloidal field (PF) coil. During the operation of the device, the operational parameter of device should be checked by technical diagnosis. This paper describes the design of circuit for checldng short between every two parts of the HT7U device. The main contents of design include circuit of data acquisition and data processing of computer.

Hydraulic Circuit Design and Dynamic Learning Using Case-based Reasoning

This paper describes the design and implementation of a hydraulic circuit design system using case-based reasoning (CBR) paradigm from AI community The domain of hydraulic circuit design and case-based reasoning are briefly reviewed Then a proposed methodology in compuer-aided circuit design and dynamic leaning with the use of CBR is described Finally an application example is selected to illustrate the ussfulness of applying CBR in hydraulic circuit design with leaming.

Toward predictable universal genetic circuit design

In thepast 2decades,synthetic biologists have applied systematic engineering principles to genetic circuit design to devise biological systems with bespoke behaviors,such as Boolean logic gates,signal filters,oscillators,state machines,perceptrons,and genetic controllers[1,2].Following a bottom-up strategy,the genetic circuits are designed by assembling a set of well-characterized biological components,or genetic parts[3],and optimized through the iterative Design-Build-Test-Learn(DBTL)cycles.

Static CMOS Implementation of Logarithmic Skip Adder

Circuit design of 32 bit logarithmic skip adder (LSA) is introduced to implement high performance,low power addition.ELM carry lookahead adder is included into groups of carry skip adder and the hybrid structure costs 30% less hardware than ELM.At circuit level,a carry incorporating structure to include the primary carry input in carry chain and an 'and xor' structure to implement final sum logic in 32 bit LSA are designed for better optimization.For 5V,1μm process,32 bit LSA has a critical delay of 5 9ns and costs an area of 0 62mm 2,power consumption of 23mW at 100MHz.For 2 5V,0 25μm process,critical delay of 0 8ns,power dissipation of 5 2mW at 100MHz is simulated.

Optimization of Global Signal Networks for Island-Style FPGAs

We present a staggered buffer connection method that provides flexibility for buffer insertion while designing global signal networks using the tile-based FPGA design methodology. An exhaustive algorithm is used to analyze the trade-off between area and speed of the global signal networks for this staggered buffer insertion scheme, and the criterion for determining the design parameters is presented. The comparative analytic result shows that the methods in this paper are proven to be more efficient for FPGAs with a large array size.