A Novel Clock Feedthrough Frequency Compensation for Fast-Settling of Folded-Cascode OTA

Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method for a folded-cascode OTA is proposed. The damping factor r/is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling. Research results indicate that the settling time of the compensated OTA is reduced by 22.7% ;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns： for VGA application, fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.

Automatic compensation of magnetic field for a rubidium space cold atom clock

When the cold atom clock operates in microgravity around the near-earth orbit, its performance will be affected by the fluctuation of magnetic field. A strategy is proposed to suppress the fluctuation of magnetic field by additional coils, whose current is changed accordingly to compensate the magnetic fluctuation by the linear and incremental compensation. The flight model of the cold atom clock is tested in a simulated orbital magnetic environment and the magnetic field fluctuation in the Ramsey cavity is reduced from 17 nT to 2 nT, which implied the uncertainty due to the second order Zeeman shift is reduced to be less than 2×10^（-16）. In addition, utilizing the compensation, the magnetic field in the trapping zone can be suppressed from 7.5 μT to less than 0.3 μT to meet the magnetic field requirement of polarization gradients cooling of atoms.

A bootstrapped switch employing a new clock feed-through compensation technique

Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feedthrough compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.