A Co-Verification Interface Design for High-Assurance CPS

Cyber-Physical Systems(CPS)tightly integrate cyber and physical components and transcend traditional control systems and embedded system.Such systems are often mission-critical;therefore,they must be high-assurance.Highassurance CPS require co-verification which takes a comprehensive view of the whole system to verify the correctness of a cyber and physical components together.Lack of strict multiple semantic definition for interaction between the two domains has been considered as an obstacle to the CPS co-verification.A Cyber/Physical interface model for hierarchical a verification of CPS is proposed.First,we studied the interaction mechanism between computation and physical processes.We further classify the interaction mechanism into two levels:logic interaction level and physical interaction level.We define different types of interface model according to combinatorial relationships of the A/D(Analog to Digital)and D/A(Digital to Analog)conversion periodical instants.This interface model has formal semantics,and is efficient for simulation and formal verification.The experiment results show that our approach has major potential in verifying system level properties of complex CPS,therefore improving the high-assurance of CPS.

Hardware/software co-verification platform for EOS design

Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

A HW/SW Co-Verification Technique for FPGA Test

Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.

A Co-verification Method Based on TWCNP-OS for Two-way Cable Network SOC

Co-verification is the key step of software and hardware codesign on SOC. This paper presents a hw/sw co-verification methodology based on TWCNP-OS, a Linux-based operating system designed for FPGA-based platform of two-way cable network (TWCNP) SOC. By implementing HAL (hardware Abstraction level) specially, which is the communications interface between hardware and software, we offer a homogeneous Linux interface for both software and hardware processes. Hardware processes inherit the same level of service from kernel, as typical Linux software processes by HAL. The familiar and language independent Linux kernel interface facilitates easy design reuse and rapid application development. The hw/sw Architecture of TWCNP and design flow of TWCNP-OS are presented on detail. A software and hardware co-verification method using TWCNP-OS is proposed, through the integrated using of Godson-I test board and TWCNP, which realizes the combination of design and verification. It is not a replacement of the co-verification with generic RTOS modeling, but is complementary to them. Performance analysis of our current implementation and our experience with developing this system based on TWCNP-OS will be presented. Most importantly, since the introduction of TWCNP-OS to our FPGA-based platform, we have observed increased productivity among high-level application developers who have little experience in FPGA application design.