A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.

Compensation of Parasitic Capacitance of Quartz Tuning Fork in AFM

We have built an atomic force microscope using a quartz tuning fork as sensor. The excitation method we adopted, the electrical excitation, introduces stray capacitance into the signal-processing circuit. In this report, we demonstrated a simple but effective method to compensate for this parasitic capacitance by adding a compensator circuit consisting of an inverting amplifier and a capacitor. The capacitor is connected in series with the inverting amplifier and the compensator is connected in parallel with the quartz tuning fork. The resonance curve of the system measured after adding the homemade compensator resembles that of a pure RLC circuit, meaning that the stray capacitance is successfully eliminated. Furthermore, we tried to use our equipment to measure PDMS sample and got clean data. This system can be further combined with confocal microscope and diamond with NV defect to build scanning NV magnetometry.

Design of compensation pixel circuit with In-Zn-O thin film transistor for active-matrix organic light-emitting diode 3D display

This paper presents a new compensation pixe] circuit suitable for active-matrix organic light-emitting diode （AMOLED） stereoscopic three dimensional （3D~ displays with shutter glasses. The simultaneous emissio~ method was used to solve the crosstalk problem, in which the periods of initialization and threshold voltage detectio11 occur for each pixel of whole panel simultaneously. Furthermore, there was no need of the periods of initialization and threshold voltage detection from the second frame beginning by one-time detection method. employing threshold voltage The non-uniformity of the proposed pixel circuit was considerably low with an average value of 8.6% measured from 20 discrete proposed pixel circuits integrated by In-Zn-O thin film transistors （IZO TFTs）. It was shown that the OLED current almost remains constant for the number of frames up to 70 even the threshold voltage detection period only exists in the first frame.

A high-precision synchronization circuit for clock distribution

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm2, and the power consumption is 1.64 mW at 500 MHz.