C-CORE:Clustering by Code Representation to Prioritize Test Cases in Compiler Testing

Edge devices,due to their limited computational and storage resources,often require the use of compilers for program optimization.Therefore,ensuring the security and reliability of these compilers is of paramount importance in the emerging field of edge AI.One widely used testing method for this purpose is fuzz testing,which detects bugs by inputting random test cases into the target program.However,this process consumes significant time and resources.To improve the efficiency of compiler fuzz testing,it is common practice to utilize test case prioritization techniques.Some researchers use machine learning to predict the code coverage of test cases,aiming to maximize the test capability for the target compiler by increasing the overall predicted coverage of the test cases.Nevertheless,these methods can only forecast the code coverage of the compiler at a specific optimization level,potentially missing many optimization-related bugs.In this paper,we introduce C-CORE(short for Clustering by Code Representation),the first framework to prioritize test cases according to their code representations,which are derived directly from the source codes.This approach avoids being limited to specific compiler states and extends to a broader range of compiler bugs.Specifically,we first train a scaled pre-trained programming language model to capture as many common features as possible from the test cases generated by a fuzzer.Using this pre-trained model,we then train two downstream models:one for predicting the likelihood of triggering a bug and another for identifying code representations associated with bugs.Subsequently,we cluster the test cases according to their code representations and select the highest-scoring test case from each cluster as the high-quality test case.This reduction in redundant testing cases leads to time savings.Comprehensive evaluation results reveal that code representations are better at distinguishing test capabilities,and C-CORE significantly enhances testing efficiency.Across four datasets,C-CORE increases the average of the percentage of faults detected(APFD)value by 0.16 to 0.31 and reduces test time by over 50% in 46% of cases.When compared to the best results from approaches using predicted code coverage,C-CORE improves the APFD value by 1.1% to 12.3% and achieves an overall time-saving of 159.1%.

危险化学品重大危险源辨识分级系统V1.0的研究与实现

危险化学品的存在给人们的生命和财产带来了潜在的风险,因此,开发一款能快速准确识别危险化学品重大危险源并进行风险分级评估的软件,对保障人民群众的生命安全和防止危险化学品事故的发生至关重要。基于MATLAB Compiler开发了危险化学品重大危险源辨识分级系统V1.0,该系统能够快速识别危险化学品的临界量和校正系数,并通过输入实际存在量,完成危险化学品的重大危险源辨识。同时,该系统还能够根据用户输入的校正系统,计算重大危险源分级指标。该系统具有操作简单、响应速度快、准确度高等优点,在危险化学品生产、储存、运输等领域有着广泛的应用前景。

Optimization and Deployment of Memory-Intensive Operations in Deep Learning Model on Edge

As a large amount of data is increasingly generated from edge devices,such as smart homes,mobile phones,and wearable devices,it becomes crucial for many applications to deploy machine learning modes across edge devices.The execution speed of the deployed model is a key element to ensure service quality.Considering a highly heterogeneous edge deployment scenario,deep learning compiling is a novel approach that aims to solve this problem.It defines models using certain DSLs and generates efficient code implementations on different hardware devices.However,there are still two aspects that are not yet thoroughly investigated yet.The first is the optimization of memory-intensive operations,and the second problem is the heterogeneity of the deployment target.To that end,in this work,we propose a system solution that optimizes memory-intensive operation,optimizes the subgraph distribution,and enables the compiling and deployment of DNN models on multiple targets.The evaluation results show the performance of our proposed system.

Algorithms for Pre-Compiling Programs by Parallel Compilers

The paper addresses the challenge of transmitting a big number offiles stored in a data center(DC),encrypting them by compilers,and sending them through a network at an acceptable time.Face to the big number offiles,only one compiler may not be sufficient to encrypt data in an acceptable time.In this paper,we consider the problem of several compilers and the objective is tofind an algorithm that can give an efficient schedule for the givenfiles to be compiled by the compilers.The main objective of the work is to minimize the gap in the total size of assignedfiles between compilers.This minimization ensures the fair distribution offiles to different compilers.This problem is considered to be a very hard problem.This paper presents two research axes.Thefirst axis is related to architecture.We propose a novel pre-compiler architecture in this context.The second axis is algorithmic development.We develop six algorithms to solve the problem,in this context.These algorithms are based on the dispatching rules method,decomposition method,and an iterative approach.These algorithms give approximate solutions for the studied problem.An experimental result is imple-mented to show the performance of algorithms.Several indicators are used to measure the performance of the proposed algorithms.In addition,five classes are proposed to test the algorithms with a total of 2350 instances.A comparison between the proposed algorithms is presented in different tables discussed to show the performance of each algorithm.The result showed that the best algorithm is the Iterative-mixed Smallest-Longest-Heuristic(ISL)with a percentage equal to 97.7%and an average running time equal to 0.148 s.All other algorithms did not exceed 22%as a percentage.The best algorithm excluding ISL is Iterative-mixed Longest-Smallest Heuristic(ILS)with a percentage equal to 21,4%and an average running time equal to 0.150 s.

A Multi-Object Genetic Algorithm for the Assembly Line Balance Optimization in Garment Flexible Job Shop Scheduling

Numerous clothing enterprises in the market have a relatively low efficiency of assembly line planning due to insufficient optimization of bottleneck stations.As a result,the production efficiency of the enterprise is not high,and the production organization is not up to expectations.Aiming at the problem of flexible process route planning in garment workshops,a multi-object genetic algorithm is proposed to solve the assembly line bal-ance optimization problem and minimize the machine adjustment path.The encoding method adopts the object-oriented path representation method,and the initial population is generated by random topology sorting based on an in-degree selection mechanism.The multi-object genetic algorithm improves the mutation and crossover operations according to the characteristics of the clothing process to avoid the generation of invalid offspring.In the iterative process,the bottleneck station is optimized by reasonable process splitting,and process allocation conforms to the strict limit of the station on the number of machines in order to improve the compilation efficiency.The effectiveness and feasibility of the multi-object genetic algorithm are proven by the analysis of clothing cases.Compared with the artificial allocation process,the compilation efficiency of MOGA is increased by more than 15%and completes the optimization of the minimum machine adjustment path.The results are in line with the expected optimization effect.

Constructing an AI Compiler for ARM Cortex-M Devices

The diversity of software and hardware forces programmers to spend a great deal of time optimizing their source code,which often requires specific treatment for each platform.The problem becomes critical on embedded devices,where computational and memory resources are strictly constrained.Compilers play an essential role in deploying source code on a target device through the backend.In this work,a novel backend for the Open Neural Network Compiler(ONNC)is proposed,which exploits machine learning to optimize code for the ARM Cortex-M device.The backend requires minimal changes to Open Neural Network Exchange(ONNX)models.Several novel optimization techniques are also incorporated in the backend,such as quantizing the ONNX model’s weight and automatically tuning the dimensions of operators in computations.The performance of the proposed framework is evaluated for two applications:handwritten digit recognition on the Modified National Institute of Standards and Technology(MNIST)dataset and model,and image classification on the Canadian Institute For Advanced Research and 10(CIFAR-10)dataset with the AlexNet-Light model.The system achieves 98.90%and 90.55%accuracy for handwritten digit recognition and image classification,respectively.Furthermore,the proposed architecture is significantly more lightweight than other state-of-theart models in terms of both computation time and generated source code complexity.From the system perspective,this work provides a novel approach to deploying direct computations from the available ONNX models to target devices by optimizing compilers while maintaining high efficiency in accuracy performance.

IOPS:computational graph optimization based on inter-operators parallel scheduling

To improve the inference efficiency of convolutional neural networks(CNN),the existing neural networks mainly adopt heuristic and dynamic programming algorithms to realize parallel scheduling among operators.Heuristic scheduling algorithms can generate local optima easily,while the dynamic programming algorithm has a long convergence time for complex structural models.This paper mainly studies the parallel scheduling between operators and proposes an inter-operator parallelism schedule(IOPS)scheduling algorithm that guarantees the minimum similar execution delay.Firstly,a graph partitioning algorithm based on the largest block is designed to split the neural network model into multiple subgraphs.Then,the operators that meet the conditions is replaced according to the defined operator replacement rules.Finally,the optimal scheduling method based on backtracking is used to schedule the computational graph.Network models such as Inception-v3,ResNet-50,and RandWire are selected for testing.The experimental results show that the algorithm designed in this paper can achieve a 1.6×speedup compared with the existing sequential execution methods.

Research on the Significance and Problems of Heroes in the Textbook

A large number texts depicting heroes have been compiled in the ministry edition of Chinese textbooks in junior high school,such as Deng Jiaxian,a scientist who has ardent love for the motherland and is fearless of difficulties and dangers;Wen Yiduo,a patriot who is devoted to study and has a strong sense of righteousness;Ye Shengtao,a scholar who is noted for his meticulous scholarship and attends to everything personally;Alizer Buffy,an unknown old man who is devoted to tree-planting in obscurity,and so on.The analysis,understanding and reading of these heroic stories and the interpretation of the significance and value of the selection of heroic images into Chinese textbooks are conducive to grasping the core quality of Chinese courses and improving the teaching of heroic images;inheriting and carrying forward the fine civilization and historical and cultural traditions of mankind,and establishing national cultural self-confidence and pride;perfecting the value system of educators and empowering students to grow healthily;guiding teenagers with immature values to establish healthy and upward values.

作战编成作战能力量化模型

作战编成(编组)作战能力量化是作战模拟中的一个重要方面,基于五力分析的基础上,讨论了作战编成(编组)作战能力的聚合方法以及对作战影响的因素,提出了作战编成(编组)作战能力量化的静态和动态量化模型。

中国百年汉英语文辞书纵横论

一、概况中国汉英语文辞书的历史同中国英汉语文辞书的历史相仿（另文阐叙），可以用“二、一、三”来概括。所谓“二”就是从第一部汉英词典（１８１５）问世至今经历了近二百年。所谓“一”就是在其间先后出版了一百数拾部各种类汉英语文辞书。所谓“三”就是汉英语文辞...

ASIC设计技术及其发展研究

对ASIC设计的工作流程和相关工具软件进行了简要介绍,并概括了ASIC设计的发展过程和较新趋势,以促进大家对芯片设计领域的认识和了解。

深亚微米并行CRC32编码芯片的设计和实现

在分析CRC编码算法的基础上,从传统的串行编码算法着手,推导出适合高速通信的并行算法,通过FPGA(现场可编程门阵列)验证确保算法代码的逻辑功能正确;采用中芯国际simc18(180nm工艺库)实现了并行CRC32编码芯片的设计.该设计具有编码速度快、占用资源少、低功耗、易于量产等优点.

原风景对景观感知影响的量表设计与分析(英文)

Prototype landscape refers to the impressive scenes that one has experienced in his/her living environment before 20 years old.Based on the analysis of the existing literature,the authors compiled a standard scale type questionnaire by means of a field survey,which was about the influences of prototype landscape on one's landscape perception.Taking Likert scale as the main part,this questionnaire analyzed the influence of prototype landscape on landscape perception from perception,attitude,and behavior dimensions.In order to further improve its rationality,the authors tested some other aspects of this questionnaire,including logic validity,construct validity,congeniality reliability,split-half reliability,etc..The results validated that the questionnaire possessed good theoretical structure and validity target,which can evaluate various aspects of prototype landscape on one's landscape perception in an effective and reliable way.Therefore,the questionnaire put forward by this study not only enriched the studies of prototype landscape on landscape designing,but also provided an effective tool for quantitative analysis of "the influences of prototype landscape on one's landscape perception".

SystemC到HDL的研究探讨

如今,用SystemC进行硬件设计和建模已成为一种趋势。但是,VHDL和Verilog是被公认的业界标准,因此,有时就不可避免要将SystemC转换成VHDL或Verilog。本文介绍了几种比较典型的免费翻译工具,简要阐述了各自的特性并作了一个比较。如果进行较大的设计研究,选择SystemCrafter SC和Agility Compiler比较理想。

Type of CPA Firm Association with Financial Statements and Commercial Lending Judgments

This study examines whether the level of Certified Public Accounting(CPA)firm assurance associated with financial statements affects commercial lending decisions.A between-subjects behavioral experiment is used with three conditions involving different levels of CPA firm assurance—compilations,reviews,and audits.Findings indicate that neither the lenders’risk assessments of loan applicants nor their elicited probabilities of granting credit differed among the three levels of CPA firm assurance.

湖泊型风景区一体化规划编制模式探讨——以太行山龙湖风景区为例(英文)

In view of lake scenic areas with abundant tourist resources but less-developed economy,contradictions between the urgency of its tourist resource development and complexity of urban-rural planning compilation were analyzed,and also limitations summarized as insufficient time and fund.Statutory planning contents included in the integrated compilation system were elaborated,and compilation of the integrated planning for the Longhe Lake Scenic Area in the Taihang Mountains was taken for example to introduce planning concepts of the compilation technical system.Considering characteristics of the study area,"regionality" was stressed as the foundation of planning compilation,concise,convenient and practical planning compilation contents were advocated and further explained from the perspectives of compiling by layer and category.In view of this,it is necessary to apply integrated compilation mode under certain circumstances,so as to provide a new approach for the planning compilation of other regions in China and enhance economic and social development of local areas.

CAN控制器的低功耗设计

CAN总线是工业测控系统中通信方式的一种广泛而有效的解决方案。首先结合应用分析CAN总线的协议和工作原理,接着进行CAN总线控制器的模块划分和设计实现,重点阐述了当前集成电路的低功耗技术,并通过Synopsys的功耗分析工具Power Compiler对CAN总线控制器进行了低功耗优化。控制器的设计采用tsmc0.13μm工艺综合库,功能仿真和综合结果表明该控制器逻辑功能符合逻辑要求,同时动态功耗有显著下降。

基于高级综合技术的RS算法实现

随着SoC技术的不断发展以及集成应用设计规模和复杂度的不断提升,使用传统的RTL设计方法难度越来越大。高级综合技术(High-level synthesis,HLS)可以实现将C语言描述的算法级设计自动转换成HDL语言描述的寄存器级设计。使用Synphony C Compiler综合工具进行RS编、译码算法设计,利用综合工具快速的架构探索以及高效的验证方法,在综合性能、面积、功耗等要求之后,完成算法C语言到Verilog HDL语言的快速转换。这种设计方法大大缩短了设计周期。

用户定制边界扫描结构的设计与自动实现

边界扫描是一种标准化的可测性设计体系结构,已被广泛应用于板级测试、系统片上调试以及IC编程;Longtium R2+微处理器的边界扫描设计采用EDA工具BSD Compiler自动完成,缩短了设计和验证周期;主要介绍了BSD Compiler的设计流程及配置要点,并结合Longtium R2+边界扫描逻辑的具体实现方案,提出了一种利用边界扫描逻辑实现对系统内部逻辑观察与控制的机制。

嵌入式Java虚拟机性能优化技术分析

本文分析了即时编译(JIT)、预编译(Pre-compilation)及直接线索化的解释器(Direct Threaded Inter-preter)等性能优化技术,并利用JBenchmark1.0、JBenchmark2.0和AMark对分别采用这3种优化技术的嵌入式Java虚拟机进行了性能测试,根据测试结果对3种优化技术进行了系统的比较分析。