An Optimal DPM Based Energy-Aware Task Scheduling for Performance Enhancement in Embedded MPSoC

Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of computational systems is changing with the advancement in technology.Due to shrinking and smaller chip size power densities onchip are increasing rapidly that increasing chip temperature in multi-core embedded technologies.The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor(CMOS)circuits because high on-chip temperature adversely affects the life span of the chip.In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first(EA-EDF)scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip(SOC).Dynamic power management(DPM)enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration.Task migration avoids peak temperature values in the multicore system.High utilization factor(ui)on central processing unit(CPU)core consumes more energy and increases the temperature on-chip.Our technique switches the core bymigrating such task to a core that has less temperature and is in a low power state.The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core.The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works.The simulation results show the improvement in performance by optimizing 4.8%on u_(i) 9%,16%,23%and 25%at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.

Energy-Efficient Scheduling Based on Task Migration Policy Using DPM for Homogeneous MPSoCs

Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

A low-phase-noise and low-power crystal oscillator for RF tuner

A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.

A CMOS high-IF down-conversion mixer for WLAN 802.11a applications

A low noise, high conversion gain down-conversion mixer for WLAN 802.11a applications, which adopts the high intermediate frequency （IF） topology, is presented. The input radio frequency （RF）band, local oscillator（LO）frequency band and output IF are 5.15 to 5.35, 4.15 to 4.35 and 1 GHz, respectively. Source resistive degeneration technique and pseudo-differential Gilbert topology are used to achieve high linearity, and, current bleeding technique and LC resonant loads are used to acquire a low noise figure. In addition, the mixer adopts a common-source transistor pair cross-stacked with a source follow pair（CSSF）circuit as an output buffer to enhance the mixer＇s conversion gain but not deteriorate the other performances. The mixer is implemented in 0.18 μm RF CMOS（complementary metal oxide semiconductor transistor）technology and the chip area of the mixer including all bonding pads is 580 μm×1 185 μm. The measured results show that under a 1.8 V supply, the conversion gain is 10.1 dB; the input 1 dB compression point and the input-referred third-order intercept point are-3.5 and 5.3 dBm, respectively; the single side band （SSB）noise figure （NF）is 8.65 dB, and the core current consumption is 3.8 mA.

Design of Power Amplifier for mm Wave 5G and Beyond

With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper firstly explains the benefits and design implications of the hybrid beamforming structure in terms of the mmWave spectrum characteristics,energy efficiency,data rate,communication capacity,coverage and implementation technology choices.Then after reviewing the techniques to improve the power amplifier(PA)output power and efficiency,the design considerations and test results of 60 GHz and 90 GHz mmWave PAs in bulk complementary metal oxide semiconductor(CMOS)process are shown.

A 60 GHz Phased Array System Analysis and Its Phase Shifter in a 40 nm CMOS Technology

A 60 GHz phased array system for mm wave frequency in 5G is introduced and a 5 bit digitally controlled phase shifter in 40 nm CMOS technology is presented.In a phased array system,the signal to noise ratio(SNR)of the receiver is improved with the beaming forming function.Therefore,the communication data rate and distance are improved accordingly.The phase shifter is the key component for achieving the beam forming function,and its resolution and power consumption are also very critical.In the second half of this paper,an analysis of phase shifter is introduced,and a 60 GHz 5 bit digitally controlled phase shifter in 40 nm complementary metal oxide semiconductor(CMOS)technology is presented.In this presented phase shifter,a hybrid structure is implemented for its advantage on lower phase deviation while keeping comparable loss.Meanwhile,this digitally controlled phase shifter is much more compact than other works.For all 32 states,the minimum phase error is 1.5°,and the maximum phase error is 6.8°.The measured insertion loss is-20.9±1 dB including pad loss at 60 GHz and the return loss is more than 10 dB over 57-64 GHz.The total chip size is 0.24 mm^2 with 0 mW DC power consumption.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Small Area ROM Design for Embedded Applications

The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.

Path Recognition Algorithm of Tracking Robots Based on Image Sensor

Path recognition is an inevitable core technology in the development of tracking robot. In this paper,the path tracking system of tracking robot can be realized by image sensor module based on camera to obtain lane image information,and then extract the path through visual servo. The whole system can be divided into seven modules: micro control unit( MCU) processor module,image acquisition module,debugging module,motor drive module,servo drive module,speed sensor module,and voltage conversion module.In image pre-processing part,there is an introduction of binarization processing and the median filtering to strengthen the image information. About recognition algorithm,three key variables which are changed in the movement state are discussed and there are also many auxiliary algorithms that help to improve the path recognition.The experiment can verify that the whole system can accurately abstract the black guide lines from the white track and make the robot moving fast and stable by following the road parameters and conditions.

A DESIGN OF 0.25μm CMOS SWITCH

Single-Pole Double-Throw （SPDT） broadband switch has been designed in a 0.25gm Complementary Metal Oxide Semiconductor （CMOS） process. To optimize the performance of isolation and insertion loss, based on normal design, the effects of Gate Series Resistances （GSR） on insertion loss and switching time are analyzed for the first time. The compatible GSRs are chosen by the analyses. The fabricated chips were tested and the results show the switch isolation from DC （Direct Current） to 1GHz exhibits 55dB and insertion loss lower than 2.1 dB.

DESIGN AND IMPLEMENTATION OF CMOS IMAGE SENSOR

A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel ar-chitecture of Active Pixel Sensor (APS) is used in the chip,which comprises a 256×256 pixel array together with column amplifiers,scan array circuits,series interface,control logic and Analog-Digital Converter (ADC). With the use of smart layout design,fill factor of pixel cell is 43%. Moreover,a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used. The CMOS image sensor chip is implemented based on the 0.35μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.

Modeling and analysis of the HPM pulse-width upset effect on CMOS inverter

We derive analytical models of the excess carrier density distribution and the HPM （high-power mi- crowave） upset susceptibility with dependence of pulse-width, which are validated by the simulated results and experimental data. Mechanism analysis and model derivation verify that the excess carriers dominate the current amplification process of the latch-up. Our results reveal that the excess carrier density distribution in P-substrate behaves as pulse-width dependence. The HPM upset voltage threshold Vp decreases with the incremental pulse- width, while there is an inflection point which is caused because the excess carrier accumulation in the P-substrate will be suppressed over time. For the first time, the physical essence of the HPM pulse-width upset effect is pro- posed to be the excess carrier accumulation effect. Validation concludes that the lip model is capable of giving a reliable and accurate prediction to the HPM upset susceptibility of a CMOS inverter, which simultaneously consid- ers technology information, ambient temperature, and layout parameters. From the model, the layout parameter LB has been demonstrated to have a significant impact on the pulse-width upset effect： a CMOS inverter with minor LB is more susceptible to HPM, which enables us to put forward hardening measures for inverters that are immune from the HPM upset.

Optimization of CMOS Repeater Driven Interconnect RC Line Using Genetic Algorithm

In this work, optimization of complementary metal oxide semiconductor (CMOS) repeater driven interconnect resistive-capacitive (RC) line is carried out using genetic algorithm (GA). This work is aimed at powerdelay- product (PDP) minimization of RC interconnect at 180 nm technology node. The algorithm simultaneously optimizes the values of supply voltage, number of repeaters and repeater width for delay and PDP minimization. The accuracy of results obtained is verified by simulations from Cadence virtuoso tool. For delay minimization, comparison of GA results with previous results of the literature shows an improvement of 44.4% in the value of the optimal number of repeaters required. This improvement is obtained by increasing the repeater size, which also increases power dissipation, so a tradeoff has also been achieved in terms of PDP minimization. The comparison of PDP results obtained in this work, with the results at 70, 100, and 130 nm technologies from literature shows improvement in optimal number of repeaters required. The results of algorithm and simulations are in good agreement and demonstrate the validity of proposed algorithm. © 2017, Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg.

15158A SP6T RF switch based on IBM SOI CMOS technology

This paper presents the design of single-pole six-throw （SP6T） RF switch with IBM 0.18 #m SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The circuit is designed and simulated by using an idea that the total load is divided into six branches and SOI special structures. The insertion loss is less than 0.6 dB, isolation is more than 30 dB, the input power P0.1dB for 0.1 dB compression point is more than 37.5 dBm, IIP3 is more than 70 dBm, the 2nd and the 3rd harmonic compressions are more than 96 dBc, and the control voltage is （＋2.46 V, 0, -2.46 V） in the frequency from 0.1 to 2.7 GHz.

A 3-5 GHz TH-UWB transmitter in 0.18-μm RF CMOS technology

An RF transmitter is proposed for 3-5 GHz time-hopping ultra wideband（TH-UWB） wireless applications.The transmitter consists of a 4-GHz oscillator, a switch with a controllable attenuator and an output matching circuit.Through controlling the low frequency signals with time-hopping pulse position modulation（TH-PPM）, the circuit supplies TH-UWB signals and can directly drive an antenna by a transmission line.The transmitter was implemented in a 0.18-μm CMOS technology;the output amplitude is about 65 mV at a 50 ？ load from a 1.8-V supply, the return loss（S 11） at the output port is less than-10 dB, and the chip size is 0.7 × 0.8 mm2, with a power consumption of 12.3 mW.