Low-Density Parity-Check （LDPC） codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years. This paper...Low-Density Parity-Check （LDPC） codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years. This paper describes two strategies to parallelize min-sum decoding of irregular LDPC codes. The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture （CUDA） to parallelize LDPC decoding on Graphics Processing Units （GPUs）. Empirical studies on data with various scales show that the performance of these decoding processes is improved by these parallel strategies and the GPUs provide more efficient, fast implementation decoder.展开更多
基金Agilent Technology Foundation(No.912-CHN09)National Natural Science Foundation of China(No.61175110)+1 种基金National Key Basic Research and Development(973)Program of China(No.2012CB316305)National Key Projects of Science and Technology of China(No.2011ZX02101-004)
文摘Low-Density Parity-Check （LDPC） codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years. This paper describes two strategies to parallelize min-sum decoding of irregular LDPC codes. The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture （CUDA） to parallelize LDPC decoding on Graphics Processing Units （GPUs）. Empirical studies on data with various scales show that the performance of these decoding processes is improved by these parallel strategies and the GPUs provide more efficient, fast implementation decoder.
