一种FPGA⁃TDC防气泡误差编码器设计

在设计基于现场可编程门阵列(FPGA)的时间数字转换器(TDC)时,时钟偏斜等因素产生的气泡误差会造成抽头延迟链(TDL)中的延迟单元失效,导致TDC的分辨率变差。提出了一种防气泡误差编码器,通过统计抽头延迟链中发生变化的抽头个数,该编码器使抽头延迟链跳变顺序按照时间顺序映射,从而消除气泡误差的影响。利用Xilinx Virtex UltraScale+FPGA对该防气泡误差编码器的有效性进行验证,使用该编码器后,基于双端采样法的抽头延迟链TDC分辨率由3.18 ps提升至1.76 ps。实验结果表明,所提出的防气泡误差编码器能够解决气泡误差导致的延迟单元失效的问题,避免分辨率的损失。

基于粗细量化并行与TDC混合的CMOS图像传感器列级ADC设计方法

针对传统单斜式模数转换器(Analog-to-Digital Converter,ADC)和串行两步式ADC在面向大面阵CMOS(Complementary Metal Oxide Semiconductor)图像传感器读出过程中的速度瓶颈问题,本文提出了一种用于高速CMOS图像传感器的全并行ADC设计方法.该方法基于时间共享和时间压缩思想,将细量化时间提前到粗量化时间段内,解决了传统方法的时间冗余问题;同时采用插入式时间差值TDC(Time-to-Digital Converter),实现了全局低频时钟下的快速转换机制.本文基于55-nm 1P4M CMOS工艺对所提方法完成了详细电路设计和全面测试验证,在模拟电压3.3 V,数字电压1.2 V,时钟频率250 MHz,输入电压1.2~2.7 V的情况下,将行时间压缩至825 ns,ADC的微分非线性和积分非线性分别为+0.6/-0.6LSB和+1.6/-1.2LSB,信噪失真比(Signal-to-Noise-and-DistortionRatio,SNDR)为68.271 dB,有效位数(Effective Numbers Of Bits,ENOB)达到11.0489 bit,列不一致性低于0.05%.相比现有的先进ADC,本文提出的方法在保证低功耗、高精度的同时,ADC转换速率提高了87.1%以上,为高速高精度CMOS图像传感器的读出与量化提供了一定的理论支撑.

Recent advancements in continuously scalable conversion-ratio switched-capacitor converter

Switched-capacitor(SC)DC-DC converter[1]is an impor-tant alternative to inductive DC-DC converter,in terms of removing the bulky power inductor.Hence,it is widely used in low-profile,low-power applications,such as the internet of things(IoT)sensor nodes and energy harvesting[2].Mean-while,considering that capacitor has a much higher energy density than inductor,high-power applications.

Energy-Efficient Implementation of BCD to Excess-3 Code Converter for Nano-Communication Using QCA Technology

Code converters are essential in digital nano communication;therefore,a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper.A QCA clockphase-based design technique was adopted to investigate integration with other complicated circuits.Using a unique XOR gate,the recommended circuit’s cell complexity has been decreased.The findings produced using the QCADesigner-2.0.3,a reliable simulation tool,prove the effectiveness of the current structure over earlier designs by considering the number of cells deployed,the area occupied,and the latency as design metrics.In addition,the popular tool QCAPro was used to estimate the energy dissipation of the proposed design.The proposed technique reduces the occupied space by∼40%,improves cell complexity by∼20%,and reduces energy dissipation by∼1.8 times(atγ=1.5EK)compared to the current scalable designs.This paper also studied the suggested structure’s energy dissipation and compared it to existing works for a better performance evaluation.

Robust optical mode converter based on topological waveguide arrays

Optical mode converters are essential for enhancing the capacity of optical communication systems. However, fabrication errors restrict the further improvement of conventional mode converters. To address this challenge, we have designed an on-chip TE0–TE1mode converter based on topologically protected waveguide arrays. The simulation results demonstrate that the converter exhibits a mode coupling efficiency of 93.5% near 1550 nm and can tolerate a relative fabrication error of 30%. Our design approach can be extended to enhance the robustness for other integrated photonic devices, beneficial for future development of optical network systems.

ANovel Non-Isolated Cubic DC-DC Converter with High Voltage Gain for Renewable Energy Power Generation System

In recent years,switched inductor(SL)technology,switched capacitor(SC)technology,and switched inductor-capacitor(SL-SC)technology have been widely applied to optimize and improve DC-DC boost converters,which can effectively enhance voltage gain and reduce device stress.To address the issue of low output voltage in current renewable energy power generation systems,this study proposes a novel non-isolated cubic high-gain DC-DC converter based on the traditional quadratic DC-DC boost converter by incorporating a SC and a SL-SC unit.Firstly,the proposed converter’s details are elaborated,including its topology structure,operating mode,voltage gain,device stress,and power loss.Subsequently,a comparative analysis is conducted on the voltage gain and device stress between the proposed converter and other high-gain converters.Then,a closed-loop simulation system is constructed to obtain simulation waveforms of various devices and explore the dynamic performance.Finally,an experimental prototype is built,experimental waveforms are obtained,and the experimental dynamic performance and conversion efficiency are analyzed.The theoretical analysis’s correctness is verified through simulation and experimental results.The proposed converter has advantages such as high voltage gain,low device stress,high conversion efficiency,simple control,and wide input voltage range,achieving a good balance between voltage gain,device stress,and power loss.The proposed converter is well-suited for renewable energy systems and holds theoretical significance and practical value in renewable energy applications.It provides an effective solution to the issue of low output voltage in renewable energy power generation systems.

An Adaptive Control Strategy for Energy Storage Interface Converter Based on Analogous Virtual Synchronous Generator

In the DC microgrid,the lack of inertia and damping in power electronic converters results in poor stability of DC bus voltage and low inertia of the DC microgrid during fluctuations in load and photovoltaic power.To address this issue,the application of a virtual synchronous generator(VSG)in grid-connected inverters control is referenced and proposes a control strategy called the analogous virtual synchronous generator(AVSG)control strategy for the interface DC/DC converter of the battery in the microgrid.Besides,a flexible parameter adaptive control method is introduced to further enhance the inertial behavior of the AVSG control.Firstly,a theoretical analysis is conducted on the various components of the DC microgrid,the structure of analogous virtual synchronous generator,and the control structure’s main parameters related to the DC microgrid’s inertial behavior.Secondly,the voltage change rate tracking coefficient is introduced to adjust the change of the virtual capacitance and damping coefficient flexibility,which further strengthens the inertia trend of the DC microgrid.Additionally,a small-signal modeling approach is used to analyze the approximate range of the AVSG’s main parameters ensuring system stability.Finally,conduct a simulation analysis by building the model of the DC microgrid system with photovoltaic(PV)and battery energy storage(BES)in MATLAB/Simulink.Simulation results from different scenarios have verified that the AVSG control introduces fixed inertia and damping into the droop control of the battery,resulting in a certain level of inertia enhancement.Furthermore,the additional adaptive control strategy built upon the AVSG control provides better and flexible inertial support for the DC microgrid,further enhances the stability of the DC bus voltage,and has a more positive impact on the battery performance.

CTC/TDCS调度命令内容安全卡控技术研究

针对调度员在CTC/TDCS系统发布调度命令时常见的错发、漏发等问题,研究调度命令安全卡控过程及方法。依据调度命令模板库和业务关键词库,归纳调度命令业务类型识别策略;基于正则表达式识别、基础数据匹配、关键词辅助定位算法,实现调度命令文本信息的有效提取;通过设计标准基础数据拓扑结构与逻辑校核算法,计算线路业务信息的准确性,评判调度命令业务数据的有效性以及业务传达操作的规范性。经验证,调度命令内容安全卡控技术能够有效识别业务信息,并辅助调度员进行二次校核,不仅提高了调度命令的准确性,也有效降低了调度员的劳动强度,满足铁路运输调度的实际应用需求。

TDCS信号检测及基函数周期估计

为了解决变换域通信系统(transformed domain communication system, TDCS)信号检测及参数估计问题,通过对TDCS信号自相关函数的推导分析,提出了一种基于二次自相关的TDCS信号检测及基函数估计的方法。分析发现,TDCS信号的自相关函数会出现周期性谱峰,且峰峰间距为基函数周期的二分之一,故以谱峰间隔是否呈现周期性作为TDCS信号的存在性判据,并根据峰峰距离进一步估计TDCS信号的基函数周期。但单次自相关处理得到的局部谱峰受信道噪声影响大,为此提出了二次自相关法,该方法使得局部峰值特征进一步加强,相较于单次自相关,二次自相关可在更低的信噪比下实现TDCS信号检测并对基函数周期进行有效估计。

一种12 bit 200 MS/s低功耗SAR-TDC ADC

为了满足低电压条件下高速高精度采样需求,设计了一种电压-时域两级混合结构流水线模数转换器(ADC)。该流水线ADC的第一级逐次逼近型(SAR)ADC将电压转换为8 bit数字,残差电压变换为时域延时信息后,第二级4.5 bit时间数字转换器(TDC)将延时转换,最终校准输出,实现12 bit精度转换。通过采用多电压供电、改进残差电压转移和放大器结构,以及优化时间判决器,提升了ADC的动态性能和采样速度,降低了采样功耗。该ADC基于40 nm CMOS工艺设计和仿真。采样率为200 MS/s时,功耗为9.5 mW,动态指标SNDR、SFDR分别达到68.4 dB、83.6 dB,优值为22 pJ·conv^(-1)·step^(-1),能够满足低功耗高速采样的应用需求。

基于SMIC 180nm工艺的内插延时链型TDC芯片

在高能同步辐射光源的高分辨谱学线站系统(HEPS-B5)的核共振散射实验中,为满足测试样品对时间数字转换皮秒级的高分辨率时间测量要求,基于SMIC 180 nm工艺设计了一款内插延时链型的四通道时间数字转换器(TDC)芯片。该TDC芯片采用“粗计数”和“细计数”相结合的链状结构,通过内插延时链法来提高测量分辨率,并结合时钟计数器以实现较大的动态测量范围。为了阻止亚稳态的传递,使用两级反相器作为基本延时单元,另外通过异步先进先出(FIFO)缓冲器实现数据在不同时钟域之间的安全传递。实验测试结果表明,该TDC芯片的时间分辨率可达到56.3 ps,动态测量范围为0~262μs,能够满足核共振散射实验的高精度时间测量要求。

基于TDC的MVT高速采集方法研究

针对目前ADC采样存在的集成化、成本和功耗相互制约等问题,实现了一种基于TDC的多通道高速采样方法,精度不受ADC采样位宽限制,只与所用FPGA芯片的硬件参数和软件设计有关,且采样通道数只与可配置的LVDS口的数量和FPGA芯片资源大小相关。与传统ADC采样方法不同,首先,设计采集电路,用已知连续阈值信号作比较器阈值电压,TDC记录信号越过阈值时间获得采样点;其次,探究阈值信号和比较器对采样信号的影响,统计各影响因素的误差并寻找最优解;最后,总结采样规律并分析其适用性。

一种TDCS信号检测及基函数周期估计的方法

针对变换域通信系统(Transform Domain Communication System,TDCS)信号难以检测的问题,设计了基于功率谱二次处理的检测方法。通过数学建模,理论推导了TDCS信号的自相关函数,并由此推出了TDCS信号的两次功率谱函数,证明了TDCS信号的二次功率谱存在周期性谱峰的特征,并给出了谱峰周期与基函数周期的数学关系。据此设计了一种TDCS信号检测算法,该算法能够检测TDCS信号并对基函数周期给予估计。理论分析了高斯白噪声对检测算法的影响,通过计算机仿真,验证了该算法在低信噪比下的性能,对比了二次功率谱法与时域相关法的检测性能,验证了采样数据长度对检测性能的影响。仿真结果表明在低信噪比条件下,本文算法对基函数周期估计仍有效,且算法性能相较于自相关法提高了约1.5 dB,增加采样数据长度可进一步提高二次功率谱算法的准确性。

基于TDC的二级频率标准驯服算法

利用全球定位系统(GPS)接收到的秒脉冲(1PPS),对常见的二级频率源温补晶振(TCXO)和相干布局囚禁(CPT)原子钟驯服开展研究。设计了硬件锁相环的驯服方案,利用时间数字转换器(TDC)测量本地分频1PPS与GPS接收机收到的1PPS时间差,实现本地信号相对GPS时间信号的锁定。锁定之后,TCXO实现了万秒稳定度为8.5×10^(-12),驯服后3.5×10^(4)s的平均频率准确度提升至5倍以上。此外,深入研究了CPT原子钟的噪声模型,在Matlab上对其进行仿真,建立起频率白噪声和频率随机游走噪声在阿伦方差曲线上的对应关系,对比了平均滤波和平均滤波+卡尔曼滤波2种滤波测频方案对CPT原子钟的驯服效果,频率稳定度在5×10^(4)s时有一个数量级的提升。

基于FPGA与TDC-GPX2的数字延时发生器设计

传统的用于LIBS检测系统的延时发生器虽然具有较高的延时精度,但是存在体积较大、价格较高的缺陷,设计出一种基于FPGA与TDC-GPX2结合的、成本较低、能够满足LIBS使用的数字延时发生器是十分必要的。该延时器以FPGA为核心处理器,结合了等离子体光电检测电路模块、脉宽检测模块、按键输入模块、高速比较电路,FPGA内部通过计数器延时原理将信号进行延时,用外置键盘设置其延时量,时间测量模块测量延时前后两路信号时间差进行验证。实验测得的数据和结果表明,该数字延时发生器输出信号的上升沿小于4 ns,下降沿小于3 ns,延时精度较高,工作性能稳定,可以满足实际应用需求。

真双极VSC-MTDC风场侧换流站软切换控制策略

真双极多端柔性直流输电(voltage source converter based multi-terminal direct current,VSC-MTDC)新能源侧换流站正、负极换流器可独立控制。针对定交流电压幅值频率控制(U/f控制)换流器发生故障,将定有功无功控制(P/Q控制)换流器的控制策略转换为定U/f控制时交直流母线电压波动较大,严重时可能会造成新能源场站脱网这一问题,建立统一切换控制模型,在统一切换控制模型基础上引入基于电流跟随的软切换控制策略,实现切换瞬间内环电流参考值同步。基于PSCAD/EMTDC搭建大规模新能源接入的四端真双极VSC-MTDC系统,经稳态、风电场功率波动、换流器单极闭锁运行工况下的仿真,验证了换流站对新能源接入的电压支撑和系统切换过程中电力系统平滑过渡的能力,为进一步提高真双极VSC-MTDC系统控制灵活性提供了参考。

Overview of Precious Metal Content Analysis Methods in Automotive Catalytic Converter

With the increasing awareness of environmental protection, people’s concern of pollution issues arising. Vehicles, as the most important means of transportation, its exhaust emission has received considerable attention. The catalytic converter is able to purify harmful substances in exhaust gas. The absolute content of precious metals in the catalytic converter dominates the exhaust gas purification effect. Accurate detection of precious metal content is of great significance for controlling the cost of catalysts, ensuring catalytic performance and recovering precious metals from spent catalysts. We herein summarized several instruments for precious metals content exploration, such as X-ray fluorescence spectrometer (XRF), atomic absorption spectrometer (AAS), inductively coupled plasma emission spectrometer (ICP) and spectrophotometer. In this thesis, the feasibility of using various devices for characterizing precious metal content in catalytic converters is analyzed and their strengths or weaknesses are elaborated.

一种用于TDC的低功耗多相时钟生成电路

在无人机3D地形测绘中,作为核心模块的时间数字转换器(TDC)需要具有远距离测量能力和高测量分辨率。基于对测距系统的长续航、公里级测距能力和厘米级测量精度的综合考量,文章设计了一种用于TDC的低功耗多相位时钟生成电路。采用了伪差分环形压控振荡器,通过优化交叉耦合结构,在保证低功耗的前提下,提升了信号边缘的斜率,增强了时钟的抖动性能和对电源噪声的抑制能力。在电荷泵设计中,通过对环路带宽的考量选取了极低的偏置电流,在进一步降低功耗的同时缩小了环路滤波器的面积。基于SMIC 180 nm CMOS工艺完成了对多相时钟生成电路的设计。仿真结果表明,在400 MHz的输出频率下,环路带宽稳定在1 MHz。该电路在不同工艺角下均能达到较快的锁定速度,相位噪声为-88 dBc@1 MHz,功耗为1 mW,均方根抖动为27 ps,满足厘米级测距的精度需求。

基于STR的两级差分的高精度低功耗TDC

随着集成电路工艺的发展和集成度的提高,电路延时显著降低,传统的时间数字转换器(TDC)的研究趋向于兼具高分辨率和高精度的电路设计。近年来,摩尔定律逐渐失效,物联网大背景下轻量化,微型化,低功耗的边缘设备得到了飞速发展,用于片上延时测量的微型化TDC的研究重点逐步转向高精度的低功耗设计。基于Xilinx Virtex-6 XC6VLX240T现场可编程门阵列(FPGA)开发平台,提出了一种以游标自定时环(vernier self timing ring,VSTR)代替直接计数法的粗测结构,和两条对称的延迟链组成的细测结构。通过边沿重合检测单元和锁存单元将粗测结构的游标STR与细测的对称延迟链结合,设计结果表明该结构量程可达到491 ns,分辨率为14.8 ps,最高精度为12.9 ps,功耗为0.068 W,说明了提出的两级差分结构具有高精度低功耗的特点。

基于TDC-GP21的恒温晶体振荡器数字化自动测试系统

针对大批量恒温晶振生产过程中繁琐的测试工序以及测试中对大量计数器的依赖,文中提出了一种基于FPGA和TDC-GP21的新型测频方法,并以此为基础设计了一款恒温晶振自动化测试平台。文中对自动测试系统的硬件实现和上位机控制软件进行了详细介绍。结合大批量恒温晶振的测试实验,验证该方法的测频精度达到了±2×10^(-10)Hz。自动测试系统取代了高度依赖计数器对恒温晶振进行测频的传统手段,实现了恒温晶振的批量测试,极大地提高了测试效率,降低了生产成本。