In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC...In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm<sup>2</sup>/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.展开更多
Residue Number System (RNS) has proved shaping the Digital Signal Processing (DSP) units into highly parallel, faster and secured entities. The computational complexity of the multiplication process for a RNS based de...Residue Number System (RNS) has proved shaping the Digital Signal Processing (DSP) units into highly parallel, faster and secured entities. The computational complexity of the multiplication process for a RNS based design can be reduced by indulging Logarithmic Number System (LNS). The combination of these unusual number systems forms Residue Logarithmic Number System (RLNS) that provides simple internal architectures. Till date RLNS based processing units are designed for binary logic based circuits. In order to reduce the number of input output signals in a system, the concept of Multiple Valued Logic (MVL) is introduced in literature. In that course of research, this paper uses Tri Valued Logic (TVL) in RLNS technique proposed, to further reduce the chip area and delay value. Thus in this research work three different concepts are proposed, it includes the design of multiplier for RLNS based application for number of bits 8, 16 and 32. Next is the utilization of TVL in the proposed multiplication structure for RLNS based system along with the error correction circuits for the ternary logarithmic and antilogarithmic conversion process. Finally the comparison of the two multiplication schemes with the existing research of multiplier design for RNS based system using booth encoding concepts. It can be found that the proposed technique using TVL saves on an average of about 63% of area occupied and 97% of delay value respectively than the existing technique.展开更多
文摘In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm<sup>2</sup>/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.
文摘Residue Number System (RNS) has proved shaping the Digital Signal Processing (DSP) units into highly parallel, faster and secured entities. The computational complexity of the multiplication process for a RNS based design can be reduced by indulging Logarithmic Number System (LNS). The combination of these unusual number systems forms Residue Logarithmic Number System (RLNS) that provides simple internal architectures. Till date RLNS based processing units are designed for binary logic based circuits. In order to reduce the number of input output signals in a system, the concept of Multiple Valued Logic (MVL) is introduced in literature. In that course of research, this paper uses Tri Valued Logic (TVL) in RLNS technique proposed, to further reduce the chip area and delay value. Thus in this research work three different concepts are proposed, it includes the design of multiplier for RLNS based application for number of bits 8, 16 and 32. Next is the utilization of TVL in the proposed multiplication structure for RLNS based system along with the error correction circuits for the ternary logarithmic and antilogarithmic conversion process. Finally the comparison of the two multiplication schemes with the existing research of multiplier design for RNS based system using booth encoding concepts. It can be found that the proposed technique using TVL saves on an average of about 63% of area occupied and 97% of delay value respectively than the existing technique.
