As a sampling technique for CCD output video signal, the correlated double sampling(CDS) technique is described as well as the filtering effects of the CDS technique on the output noise of CCD including the reset nois...As a sampling technique for CCD output video signal, the correlated double sampling(CDS) technique is described as well as the filtering effects of the CDS technique on the output noise of CCD including the reset noise of CCD, the white noise of output amplifier and 1/f noise. From real application of CDS device——TH7982A, it is concluded that the output signal-to-noise ratio of 50dB for CCD signal can be obtained.展开更多
While an auxiliary information in double sampling increases the precision of an estimate and solves the problem of bias caused by non-response in sample survey, the question is that, does the level of correlation betw...While an auxiliary information in double sampling increases the precision of an estimate and solves the problem of bias caused by non-response in sample survey, the question is that, does the level of correlation between the auxiliary information x and the study variable y ease in the accomplishment of the objectives of using double sampling? In this research, investigation was conducted through empirical study to ascertain the importance of correlation level between the auxiliary variable and the study variable to maximally accomplish the importance of auxiliary variable(s) in double sampling. Based on the Statistics criteria employed, which are minimum variance, coefficient of variation and relative efficiency, it was established that the higher the correlation level between the study and auxiliary variable(s) is, the better the estimator is.展开更多
This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer...This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD.Dual-CDS is used to reduce random noise and the nonuniformity between columns.Dual-mode counting method is proposed to improve circuit robustness.A prototype sensor was fabricated using a 0.11μm CMOS process.Measurement results show that the lag of the five-finger shaped pixel is reduced by 80%compared with the conventional rectangular pixel,the chip power consumption is only 36 mW,the dynamic range is 67.3 dB,the random noise is only 1.55 e^(-)_(rms),and the figure-of-merit is only 1.98 e^(-)·nJ,thus realizing low-power and high-quality imaging.展开更多
A new Dark Current Suppression (DCS) CMOS readout circuits for large format Quantum-Well-Infrared Photo-detector (QWIP) Focal-Plane-Array (FPA) with novel CorrelatedDouble-Sampling (CDS) structure based on dynamic sou...A new Dark Current Suppression (DCS) CMOS readout circuits for large format Quantum-Well-Infrared Photo-detector (QWIP) Focal-Plane-Array (FPA) with novel CorrelatedDouble-Sampling (CDS) structure based on dynamic source-follower are proposed, which can overcome the drawbacks of the present techniques, such as sensitive to the non-uniformity of the QWIP materials, poor readout noise features, low frame frequency, limited injection efficiency and dynamic range, etc. The dummy is adopted to realize dark current suppression, while the integration time. Through the novel CDS structure, the output waveform is boxcar, and the frame frequency is increased. Simulation results demonstrate that, in high background sense, the proposed DCS circuit can suppress the dark current, achieve good readout performance, such as low power consumption, high charge sensitivity, high resolution, large dynamic range, and insensitive to the non-uniformity of the QWIP materials.展开更多
A switched capacitor bandgap voltage reference with correlated double sampling structure embedded in a temperature sensor is implemented in a standard 0.35 um CMOS process. Due to the smaller change of the op-amp＇s o...A switched capacitor bandgap voltage reference with correlated double sampling structure embedded in a temperature sensor is implemented in a standard 0.35 um CMOS process. Due to the smaller change of the op-amp＇s output voltage, this topology is very suitable for low power applications. In addition, errors caused by the finite op-amp gain, input offset voltage, and 1/f noise are eliminated with the correlated double sampling technique. Additionally, two-level process calibration techniques are designed to minimize the process spread. Finally, a method of getting a full period valid reference voltage output is discussed and experimental results are provided to verify the effectiveness of the proposed structure.展开更多
文摘As a sampling technique for CCD output video signal, the correlated double sampling(CDS) technique is described as well as the filtering effects of the CDS technique on the output noise of CCD including the reset noise of CCD, the white noise of output amplifier and 1/f noise. From real application of CDS device——TH7982A, it is concluded that the output signal-to-noise ratio of 50dB for CCD signal can be obtained.
文摘While an auxiliary information in double sampling increases the precision of an estimate and solves the problem of bias caused by non-response in sample survey, the question is that, does the level of correlation between the auxiliary information x and the study variable y ease in the accomplishment of the objectives of using double sampling? In this research, investigation was conducted through empirical study to ascertain the importance of correlation level between the auxiliary variable and the study variable to maximally accomplish the importance of auxiliary variable(s) in double sampling. Based on the Statistics criteria employed, which are minimum variance, coefficient of variation and relative efficiency, it was established that the higher the correlation level between the study and auxiliary variable(s) is, the better the estimator is.
基金supported by the National Key R&D Program of China(2019YFB2204304).
文摘This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD.Dual-CDS is used to reduce random noise and the nonuniformity between columns.Dual-mode counting method is proposed to improve circuit robustness.A prototype sensor was fabricated using a 0.11μm CMOS process.Measurement results show that the lag of the five-finger shaped pixel is reduced by 80%compared with the conventional rectangular pixel,the chip power consumption is only 36 mW,the dynamic range is 67.3 dB,the random noise is only 1.55 e^(-)_(rms),and the figure-of-merit is only 1.98 e^(-)·nJ,thus realizing low-power and high-quality imaging.
基金Supported by the National Natural Science Foundation of China(No.60077025)
文摘A new Dark Current Suppression (DCS) CMOS readout circuits for large format Quantum-Well-Infrared Photo-detector (QWIP) Focal-Plane-Array (FPA) with novel CorrelatedDouble-Sampling (CDS) structure based on dynamic source-follower are proposed, which can overcome the drawbacks of the present techniques, such as sensitive to the non-uniformity of the QWIP materials, poor readout noise features, low frame frequency, limited injection efficiency and dynamic range, etc. The dummy is adopted to realize dark current suppression, while the integration time. Through the novel CDS structure, the output waveform is boxcar, and the frame frequency is increased. Simulation results demonstrate that, in high background sense, the proposed DCS circuit can suppress the dark current, achieve good readout performance, such as low power consumption, high charge sensitivity, high resolution, large dynamic range, and insensitive to the non-uniformity of the QWIP materials.
基金Project supported by the National Science and Technology Major Projects of China(No.2012ZX02503-005)the Research Program of Science and Technology Commission of Shanghai(No.11511500903)
文摘A switched capacitor bandgap voltage reference with correlated double sampling structure embedded in a temperature sensor is implemented in a standard 0.35 um CMOS process. Due to the smaller change of the op-amp＇s output voltage, this topology is very suitable for low power applications. In addition, errors caused by the finite op-amp gain, input offset voltage, and 1/f noise are eliminated with the correlated double sampling technique. Additionally, two-level process calibration techniques are designed to minimize the process spread. Finally, a method of getting a full period valid reference voltage output is discussed and experimental results are provided to verify the effectiveness of the proposed structure.
