Gigahertz frequency hopping in an optical phase-locked loop for Raman lasers

Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.

11.6-GHz 0.18-μm monolithic CMOS phase-locked loop

A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

An improved arctangent algorithm based on phase-locked loop for heterodyne detection system

We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

Phase-Locked Loop Based Cancellation of ECG Power Line Interference

Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Noise Reduction for Digital Communications—The Masterpiece, a Modified Costas Loop

An efficient way of noise reduction has been presented: A modified Costas loop called as Masterpiece. The basic version of the Costas loop has been developed for SSB SC demodulation, but the same circuit can be applied for QAM (quadrature amplitude modulation) demodulation as well. Noise sensitivity of the basic version has been decreased. One trick is the transformation of the real channel input into complex signal, the other one is the application of our folding algorithm. The result is that the Masterpiece provides a 4QAM symbol error rate (SER) of 6 × 10−4 for input signal to noise ratio (SNR) of −1 dB. In this paper, an improved version of the original Masterpiece is introduced. The complex channel input signal is normalized, and rotational average is applied. The 4QAM result is SER of 3 × 10−4 for SNR of −1 dB. At SNR of 0 dB, the improved version produces 100 times better SER than that the original Costas loop does. In our times, this topic has a special importance because by application of our Masterpiece, all dangerous field strengths from 5G and WiFi, could be decreased by orders of magnitude. The Masterpiece can break the Shannon formula.

Comparative Study of Low-Pass Filter and Phase-Locked Loop Type Speed Filters for Sensorless Control of AC Drives

High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.

Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop

We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10?9 and a dynamic locking accuracy of about 5 × 10?8 are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on.

改进的数字Costas环设计与实现

为解决传统Costas环在多路载波提取中占用资源量大以及在数字下变频中消耗现场可编程门阵列资源过多的问题,提出一种采用逻辑控制模块代替直接数字合成器模块的方法,设计并实现数字Costas环路。该方法适用于阵列雷达信号等多路载波信号处理,能够实现环路载波的快速提取,节约25%的硬件资源。

Costas环在无线扩频定位系统中的应用技术研究

分析了扩频定位系统中载波恢复和数据解调数学模型,设计了环路中应用的Butterworth低通滤波器和产生正交两路信号的Hilbert变换滤波器,在Simulink中建立了Costas环仿真模型。结果表明:该Costas环能够准确地实现扩频定位系统的载波恢复和发送端数据解调输出,理论仿真和实际工程实验基本一致。

锁相环与锁频环在数字Costas环中的应用

基于锁相环和锁频环的模型,研究了由两者构成的数字Costas环结构和性能。首先介绍了传统的数字Costas环模型,接着给出了鉴相器、二阶环路滤波器和三阶环路滤波器的结构,在此基础上分析了基于锁频环的数字Costas模型,实现了扩大Costas环的跟踪范围和提高跟踪精度的目的,最后给出了仿真结果,分析了两种环路单独和相结合后的应用和特点。

大多普勒频偏SOQPSK信号FFT引导COSTAS环载波跟踪技术

SOQPSK信号包络恒定、相位连续,拥有很高的功率、频谱效率,在卫星通信、深空通信、航空遥测等系统中具有广泛的应用前景.为保证SOQPSK信号能够适应上述系统较大的载波多普勒平移,本文提出一种FFT引导COSTAS环的SOQPSK信号载波跟踪技术.算法首先利用FFT粗略估计多普勒频率,将载波频偏牵引至较小的误差范围,再利用改进的COSTAS环跟踪载波残差及相位误差,进而实现了对大频偏SOQPSK信号载波的稳态跟踪.仿真结果表明,本文所提算法不仅能够跟踪大频偏载波,而且在小频偏时性能亦优于传统方法.

数字Costas环在FPGA中的实现

Costas环是一种闭环自动调整系统,常用于抑制载波的相位调制系统中提取参考载波信号.文中介绍了Costas环的基本原理,提出了一种用CIC滤波器代替环路滤波器的方法,并根据该原理用matlab的simulink工具箱对costas环进行了建模和仿真,最后在Quartus II+ModelSim环境中用Verilog语言实现了该算法,并下载到软件无线电硬件电路中验证了该算法的正确性.仿真和实验结果表明,该Costas环路具有十分优良的性能.

数字Costas环的设计与实现

针对扩频系统的载波同步,研究了数字Costas环的设计和实现方法。介绍了数字Costas环的结构、实现载波同步的基本方法。以二阶环为例,分析了数字锁相环的环路滤波器的参数设计方法,为数字Costas环的设计提供了参考。提出了在高速信号处理板(以FPGA和DSP为基础)中数字Costas环的实现方案,经工程验证,能够实现载波同步,解调出所需信号。

适用于高阶QAM的改进型Costas环研究

为提高高阶正交幅度调制(QAM)解调中载波恢复的收敛速度及跟踪稳定性,基于软件无线电设计思路和传统科斯塔斯(Costas)环基本原理,提出一种改进型Costas环的研究方法。该方法采用符号鉴相器代替传统的乘法器鉴相器,设计的环路滤波器运用多系数调整取代传统的一组系数调整。以1024QAM信号解调为例,通过使用Matlab/Simulink下的System Generator工具箱对解调系统建模仿真,以验证其载波恢复性能。仿真结果表明,改进的Costas环能准确地对接收的高阶QAM信号进行载波恢复,且与传统算法相比,改进后的环路跟踪平稳、收敛速度更快速、误码率更低,较好地改善了通信质量。

基于FPGA的数字Costas锁相环路的设计

介绍了应用EDA技术设计嵌入式全数字Costas锁相环路的方法.建立了连续域环路线性模型,给出环路方程,并利用连续域和离散的变换关系,即L aplace变换和Z变换的关系,由连续域环路的线性相位模型推导出了离散域环路的线性相位模型,由此来讨论二阶Costas环路在离散域实现方法,讨论了离散域中环路滤波器的传递函数及实现,讨论了DCO的离散设计方法及实现,并采用从逻辑电路的顶层到底层以及模块化的设计思想,用VHDL 编程语言,通过逻辑综合和仿真,可编程逻辑器件FPGA予以实现.