By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is su...By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.展开更多
By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric...By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.展开更多
Simulating the total ionizing dose(TID)of an electrical system using transistor-level models can be difficult and expensive,particularly for digital-integrated circuits(ICs).In this study,a method for modeling TID eff...Simulating the total ionizing dose(TID)of an electrical system using transistor-level models can be difficult and expensive,particularly for digital-integrated circuits(ICs).In this study,a method for modeling TID effects in complementary metaloxide semiconductor(CMOS)digital ICs based on the input/output buffer information specification(IBIS)was proposed.The digital IC was first divided into three parts based on its internal structure:the input buffer,output buffer,and functional area.Each of these three parts was separately modeled.Using the IBIS model,the transistor V-I characteristic curves of the buffers were processed,and the physical parameters were extracted and modeled using VHDL-AMS.In the functional area,logic functions were modeled in VHDL according to the data sheet.A golden digital IC model was developed by combining the input buffer,output buffer,and functional area models.Furthermore,the golden ratio was reconstructed based on TID experimental data,enabling the assessment of TID effects on the threshold voltage,carrier mobility,and time series of the digital IC.TID experiments were conducted using a CMOS non-inverting multiplexer,NC7SZ157,and the results were compared with the simulation results,which showed that the relative errors were less than 2%at each dose point.This confirms the practicality and accuracy of the proposed modeling method.The TID effect model for digital ICs developed using this modeling technique includes both the logical function of the IC and changes in electrical properties and functional degradation impacted by TID,which has potential applications in the design of radiation-hardening tolerance in digital ICs.展开更多
This paper proposes a simplification method for realization of current-mode multivalued CMOS circuits. The key of this method is to find a cover on the K-map for a given multivalued function, which fits to the realiza...This paper proposes a simplification method for realization of current-mode multivalued CMOS circuits. The key of this method is to find a cover on the K-map for a given multivalued function, which fits to the realization of current-mode CMOS circuits. The design example shows that the design presented in this paper is better than the design proposed by G. W. Dueck et al. (1987).展开更多
Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer i...Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.展开更多
该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μ...该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μm CMOS工艺研制了5G毫米波反向阵芯片,包括发射前端、接收前端及跟踪锁相环等核心模块,其中发射及接收前端芯片采用次谐波混频及跨导增强等技术,分别实现了19.5 d B和18.7 d B的实测转换增益。所实现的跟踪锁相环芯片具备双模工作优势,可根据不同参考信号支持幅度调制及相位调制,实测输出信号相噪优于–125 dBc/Hz@100 kHz。该文给出的测试结果验证了所提5G毫米波反向阵通信架构及其CMOS芯片实现的可行性,从而为5G/6G毫米波通信探索了一种架构极简、成本极低、拓展性强的新方案。展开更多
To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and intern...To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and internal node state, we find the deficiency of only using port information. Then, we define the gate level number computing method and the concept of slice, and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information. Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model, and maintain a 700 ＋ speedup compared with the existing gate-level power analysis technique.展开更多
A simple and successful method for the stability enhancement of integrated circuits is presented. When the process parameters, temperature, and supply voltage are changed, according to the simulation results, this met...A simple and successful method for the stability enhancement of integrated circuits is presented. When the process parameters, temperature, and supply voltage are changed, according to the simulation results, this method yields a standard deviation of the transconductance of MOSFETs that is 41.4% less than in the uncompensated case. This method can be used in CMOS LC oscillator design.展开更多
New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study o...New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.展开更多
This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the t...This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.展开更多
基金Supported by National Natural Science Foundation of China
文摘By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.
基金National Natural Science Foundation of ChinaNatural science Foundation of Zhejiang Province
文摘By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.
基金This work was supported by the special fund of the State Key Laboratory of Intense Pulsed Radiation Simulation and Effect(No.SKLIPR2011).
文摘Simulating the total ionizing dose(TID)of an electrical system using transistor-level models can be difficult and expensive,particularly for digital-integrated circuits(ICs).In this study,a method for modeling TID effects in complementary metaloxide semiconductor(CMOS)digital ICs based on the input/output buffer information specification(IBIS)was proposed.The digital IC was first divided into three parts based on its internal structure:the input buffer,output buffer,and functional area.Each of these three parts was separately modeled.Using the IBIS model,the transistor V-I characteristic curves of the buffers were processed,and the physical parameters were extracted and modeled using VHDL-AMS.In the functional area,logic functions were modeled in VHDL according to the data sheet.A golden digital IC model was developed by combining the input buffer,output buffer,and functional area models.Furthermore,the golden ratio was reconstructed based on TID experimental data,enabling the assessment of TID effects on the threshold voltage,carrier mobility,and time series of the digital IC.TID experiments were conducted using a CMOS non-inverting multiplexer,NC7SZ157,and the results were compared with the simulation results,which showed that the relative errors were less than 2%at each dose point.This confirms the practicality and accuracy of the proposed modeling method.The TID effect model for digital ICs developed using this modeling technique includes both the logical function of the IC and changes in electrical properties and functional degradation impacted by TID,which has potential applications in the design of radiation-hardening tolerance in digital ICs.
基金Supported by the National Natural Science Foundation of China
文摘This paper proposes a simplification method for realization of current-mode multivalued CMOS circuits. The key of this method is to find a cover on the K-map for a given multivalued function, which fits to the realization of current-mode CMOS circuits. The design example shows that the design presented in this paper is better than the design proposed by G. W. Dueck et al. (1987).
文摘Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.
文摘该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μm CMOS工艺研制了5G毫米波反向阵芯片,包括发射前端、接收前端及跟踪锁相环等核心模块,其中发射及接收前端芯片采用次谐波混频及跨导增强等技术,分别实现了19.5 d B和18.7 d B的实测转换增益。所实现的跟踪锁相环芯片具备双模工作优势,可根据不同参考信号支持幅度调制及相位调制,实测输出信号相噪优于–125 dBc/Hz@100 kHz。该文给出的测试结果验证了所提5G毫米波反向阵通信架构及其CMOS芯片实现的可行性,从而为5G/6G毫米波通信探索了一种架构极简、成本极低、拓展性强的新方案。
文摘To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and internal node state, we find the deficiency of only using port information. Then, we define the gate level number computing method and the concept of slice, and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information. Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model, and maintain a 700 ＋ speedup compared with the existing gate-level power analysis technique.
文摘A simple and successful method for the stability enhancement of integrated circuits is presented. When the process parameters, temperature, and supply voltage are changed, according to the simulation results, this method yields a standard deviation of the transconductance of MOSFETs that is 41.4% less than in the uncompensated case. This method can be used in CMOS LC oscillator design.
文摘New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
基金Supported by the National Native Science Foundation of China
文摘This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.
