Two cubical 3D electric circuits with single and double capacitors and twelve ohmic resistors are considered. The resistors are the sides of the cube. The circuit is fed with a single internal emf. The charge on the c...Two cubical 3D electric circuits with single and double capacitors and twelve ohmic resistors are considered. The resistors are the sides of the cube. The circuit is fed with a single internal emf. The charge on the capacitor(s) and the current distributions of all twelve sides of the circuit(s) vs. time are evaluated. The analysis requires solving twelve differential-algebraic intertwined symbolic equations. This is accomplished by applying a Computer Algebra System (CAS), specifically Mathematica. The needed codes are included. For a set of values assigned to the elements, the numeric results are depicted.展开更多
This report addresses the issues concerning the analysis of an electric circuit composed of multiple resistors configured in a 3-Dimension structure. Noting, all the standard textbooks of physics and engineering irres...This report addresses the issues concerning the analysis of an electric circuit composed of multiple resistors configured in a 3-Dimension structure. Noting, all the standard textbooks of physics and engineering irrespective of the used components are circuits assembled in two dimensions. Here, by deviating from the “norm” we consider a case where the resistors are arranged in a 3D structure;e.g., a cube. Although, independent of the dimension of the design the same physics principles apply, transitioning from a 2D to a 3D makes the corresponding analysis considerably challenging. In general, with no exception, depending on the used components the analysis faces with solving a set of either algebraic or differential-algebraic equations. Practically, this interfaces with a Computer Algebra System (CAS). The main objective is symbolically to identify the current distributions and the equivalent resistor (s) of cubically assembled resistors.展开更多
Three-dimensional integrated circuit technology with transistors stacked on top of one an-other in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the te...Three-dimensional integrated circuit technology with transistors stacked on top of one an-other in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the technique to obtain high performance multi-layer transistors is extraordinarily diffi-cult. Not until recently does such technology become feasible. In this paper, the background and vari-ous techniques to form three-dimensional circuits will be reviewed. Recent development of a simple and promising technology to achieve three-dimensional integration using Metal-Induced-Lateral-Crystalliza-tion will be described. Preliminary results of 3D inverters will also be provided to demonstrate the viabil-ity for 3D integration.展开更多
Propose the sequential circuits with the ternary D-ffs in series^1. Discuss the equivalence between the sequential circuits with the p-valued flip-flops in series and in parallel as a part of studying the multiple val...Propose the sequential circuits with the ternary D-ffs in series^1. Discuss the equivalence between the sequential circuits with the p-valued flip-flops in series and in parallel as a part of studying the multiple valued logic circuits.展开更多
Ordinary algebra is used to represent Boolean algebra on logic variables with states 0 and 1, so to achieve a unify approach to simulated both digital and analog circuit in PSPICE. Result on mixed A/D simulation shows...Ordinary algebra is used to represent Boolean algebra on logic variables with states 0 and 1, so to achieve a unify approach to simulated both digital and analog circuit in PSPICE. Result on mixed A/D simulation shows a save in memory but generally longer run time.展开更多
Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vert...Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.展开更多
文摘Two cubical 3D electric circuits with single and double capacitors and twelve ohmic resistors are considered. The resistors are the sides of the cube. The circuit is fed with a single internal emf. The charge on the capacitor(s) and the current distributions of all twelve sides of the circuit(s) vs. time are evaluated. The analysis requires solving twelve differential-algebraic intertwined symbolic equations. This is accomplished by applying a Computer Algebra System (CAS), specifically Mathematica. The needed codes are included. For a set of values assigned to the elements, the numeric results are depicted.
文摘This report addresses the issues concerning the analysis of an electric circuit composed of multiple resistors configured in a 3-Dimension structure. Noting, all the standard textbooks of physics and engineering irrespective of the used components are circuits assembled in two dimensions. Here, by deviating from the “norm” we consider a case where the resistors are arranged in a 3D structure;e.g., a cube. Although, independent of the dimension of the design the same physics principles apply, transitioning from a 2D to a 3D makes the corresponding analysis considerably challenging. In general, with no exception, depending on the used components the analysis faces with solving a set of either algebraic or differential-algebraic equations. Practically, this interfaces with a Computer Algebra System (CAS). The main objective is symbolically to identify the current distributions and the equivalent resistor (s) of cubically assembled resistors.
文摘Three-dimensional integrated circuit technology with transistors stacked on top of one an-other in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the technique to obtain high performance multi-layer transistors is extraordinarily diffi-cult. Not until recently does such technology become feasible. In this paper, the background and vari-ous techniques to form three-dimensional circuits will be reviewed. Recent development of a simple and promising technology to achieve three-dimensional integration using Metal-Induced-Lateral-Crystalliza-tion will be described. Preliminary results of 3D inverters will also be provided to demonstrate the viabil-ity for 3D integration.
文摘Propose the sequential circuits with the ternary D-ffs in series^1. Discuss the equivalence between the sequential circuits with the p-valued flip-flops in series and in parallel as a part of studying the multiple valued logic circuits.
文摘Ordinary algebra is used to represent Boolean algebra on logic variables with states 0 and 1, so to achieve a unify approach to simulated both digital and analog circuit in PSPICE. Result on mixed A/D simulation shows a save in memory but generally longer run time.
基金Supported by the National Natural Science Foundation of China (Nos.60833004 and 60876026)the 3-D Floorplanning and Placement Project of the Intel Corporation
文摘Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.
