HVDC transmission system has considerable impact on the surrounding power transformers when the system is running in the unipolar ground mode, which will cause the DC magnetic biasing phenomenon on transformers. This ...HVDC transmission system has considerable impact on the surrounding power transformers when the system is running in the unipolar ground mode, which will cause the DC magnetic biasing phenomenon on transformers. This problem would be more serious, after commission and operation of UHVDC transmission system in China. According to the Guangdong power grid under the influence of DC magnetic bias seriously, but little research about the using of blocking device, this paper proposed an optimization scheme about the usage of blocking device combination. Firstly, the subject studied the method of suppressing transformer neutral point DC depending on analysis the mechanism of magnetic biasing, and then found out the changes of power grid after using the capacitance blocking device which is popular used by Guangdong power grid. The particle swarm optimization (PSO) has been used to find a better way to suppress the DC in power grid, and combined with NSGA to solve the mixed integer programming problem. The final data validation of this method is valuable in engineering application.展开更多
IEC TS 60076-23,the first IEC standard on DC bias suppression devices approved by IEC/TC 14 in November 2017,is expected to be published and put into force in 2018,overcoming the lack of such IEC standards in the fiel...IEC TS 60076-23,the first IEC standard on DC bias suppression devices approved by IEC/TC 14 in November 2017,is expected to be published and put into force in 2018,overcoming the lack of such IEC standards in the field.The Shanghai branch of SGCC has carried out studies and researches on DC bias effect for more than 10 years,and it has led the standard development based on its R&D and the application of DC bias suppression devices in China.展开更多
We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor （1 T1R） resistance random access memory （RRAM） device. All the devices are operated...We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor （1 T1R） resistance random access memory （RRAM） device. All the devices are operated under the same test conditions, except for the initial formation process with different modes. Based on the statistical results, the high resistance state （FIRS） under the dc forming mode shows a lower value with better distribution compared with that under the pulse mode. One of the possible reasons for such a phenomenon originates from different properties of conductive filament （CF） formed in the resistive switching layer under two different modes. For the dc forming mode, the formed filament is thought to be continuous, which is hard to be ruptured, resulting in a lower HRS. However, in the case of pulse forming, the filament is discontinuous where the transport mechanism is governed by hopping. The low resistance state （LRS） can be easily changed by removing a few trapping states from the conducting path. Hence, a higher FIRS is thus observed. However, the HRS resistance is highly dependent on the length of the gap opened. A slight variation of the gap length will cause wide dispersion of resistance.展开更多
With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have eme...With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node.The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates.Due to the relatively more mature process and rich learning of the device physics,the FinFET is still extended to 5 nm technology node.In this paper,we proposed a 5 nm FINFET device,which is based on typical 5 nm logic design rules.To achieve the challenging device performance target,which is around 15%speed gain or 25%power reduction against the 7 nm device,we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability.Based on our preferred device architecture,we provide our brief process flow,key dimensions,and simulated device DC/AC performance,like Vt,Idsat,SS,DIBL and parasitic parameters.As a part of the final evaluation,RO simulation result has been checked,which demonstrates that the Performance Per Area(PPA)is close to industry reference 5 nm performance.展开更多
为了研究呼辽±500 k V直流输电工程主设备故障的电气特征,有效区分各主设备故障,利用电磁暂态仿真软件PSCAD/EMTDC建立了呼辽±500 k V直流输电系统的详细模型,对高压直流输电系统主设备进行了详细介绍,并在此基础上对逆变侧...为了研究呼辽±500 k V直流输电工程主设备故障的电气特征,有效区分各主设备故障,利用电磁暂态仿真软件PSCAD/EMTDC建立了呼辽±500 k V直流输电系统的详细模型,对高压直流输电系统主设备进行了详细介绍,并在此基础上对逆变侧主设备故障进行了仿真分析。仿真结果表明,交流滤波器故障后,逆变侧直流电压和电流变化很小。换流变压器故障后,逆变侧直流电压、电流持续振荡,系统失去稳定。平波电抗器发生短路故障后,逆变侧直流电流发生明显波动,且含有大量的谐波分量,逆变侧直流电压略微降低。最后,基于小波变换理论,分析和提取各故障情况下电气量的特征信息,有效地识别各类故障。展开更多
文摘HVDC transmission system has considerable impact on the surrounding power transformers when the system is running in the unipolar ground mode, which will cause the DC magnetic biasing phenomenon on transformers. This problem would be more serious, after commission and operation of UHVDC transmission system in China. According to the Guangdong power grid under the influence of DC magnetic bias seriously, but little research about the using of blocking device, this paper proposed an optimization scheme about the usage of blocking device combination. Firstly, the subject studied the method of suppressing transformer neutral point DC depending on analysis the mechanism of magnetic biasing, and then found out the changes of power grid after using the capacitance blocking device which is popular used by Guangdong power grid. The particle swarm optimization (PSO) has been used to find a better way to suppress the DC in power grid, and combined with NSGA to solve the mixed integer programming problem. The final data validation of this method is valuable in engineering application.
文摘IEC TS 60076-23,the first IEC standard on DC bias suppression devices approved by IEC/TC 14 in November 2017,is expected to be published and put into force in 2018,overcoming the lack of such IEC standards in the field.The Shanghai branch of SGCC has carried out studies and researches on DC bias effect for more than 10 years,and it has led the standard development based on its R&D and the application of DC bias suppression devices in China.
基金Supported by the National Basic Research Program of China under Grant Nos 2011CBA00602,2010CB934200,2011CB921804,2011CB707600,2011AA010401,and 2011AA010402the National Natural Science Foundation of China under Grant Nos61322408,61334007,61376112,61221004,61274091,61106119,61106082,and 61006011
文摘We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor （1 T1R） resistance random access memory （RRAM） device. All the devices are operated under the same test conditions, except for the initial formation process with different modes. Based on the statistical results, the high resistance state （FIRS） under the dc forming mode shows a lower value with better distribution compared with that under the pulse mode. One of the possible reasons for such a phenomenon originates from different properties of conductive filament （CF） formed in the resistive switching layer under two different modes. For the dc forming mode, the formed filament is thought to be continuous, which is hard to be ruptured, resulting in a lower HRS. However, in the case of pulse forming, the filament is discontinuous where the transport mechanism is governed by hopping. The low resistance state （LRS） can be easily changed by removing a few trapping states from the conducting path. Hence, a higher FIRS is thus observed. However, the HRS resistance is highly dependent on the length of the gap opened. A slight variation of the gap length will cause wide dispersion of resistance.
基金The authors would like to thank the management team and all our team members in Shanghai ICRD center.
文摘With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node.The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates.Due to the relatively more mature process and rich learning of the device physics,the FinFET is still extended to 5 nm technology node.In this paper,we proposed a 5 nm FINFET device,which is based on typical 5 nm logic design rules.To achieve the challenging device performance target,which is around 15%speed gain or 25%power reduction against the 7 nm device,we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability.Based on our preferred device architecture,we provide our brief process flow,key dimensions,and simulated device DC/AC performance,like Vt,Idsat,SS,DIBL and parasitic parameters.As a part of the final evaluation,RO simulation result has been checked,which demonstrates that the Performance Per Area(PPA)is close to industry reference 5 nm performance.
文摘为了研究呼辽±500 k V直流输电工程主设备故障的电气特征,有效区分各主设备故障,利用电磁暂态仿真软件PSCAD/EMTDC建立了呼辽±500 k V直流输电系统的详细模型,对高压直流输电系统主设备进行了详细介绍,并在此基础上对逆变侧主设备故障进行了仿真分析。仿真结果表明,交流滤波器故障后,逆变侧直流电压和电流变化很小。换流变压器故障后,逆变侧直流电压、电流持续振荡,系统失去稳定。平波电抗器发生短路故障后,逆变侧直流电流发生明显波动,且含有大量的谐波分量,逆变侧直流电压略微降低。最后,基于小波变换理论,分析和提取各故障情况下电气量的特征信息,有效地识别各类故障。
