The conventional inverters have the shortcomings of straightway conduction in transistors and the difficulty of realizing soft swit￣ching. A novel inverter based on the DC/DC converter topology is presented. The inve...The conventional inverters have the shortcomings of straightway conduction in transistors and the difficulty of realizing soft swit￣ching. A novel inverter based on the DC/DC converter topology is presented. The inverter is comprised of a combined Buck/Boost DC/DC converter and a bridge circuit. The front stage converter is controlled to output variable DC voltage and the bridge circuit is used to convert the DC voltage to AC output. The energy feedback technology and one circle control scheme are used t...展开更多
A DC DC buck converter c on trolled by naturally sampled, constant frequency PWM is considered. The existe nce of chaotic solutions and the output performance of the system under differen t circuit parameters are s...A DC DC buck converter c on trolled by naturally sampled, constant frequency PWM is considered. The existe nce of chaotic solutions and the output performance of the system under differen t circuit parameters are studied. The transforming pattern of system behavior fr om steady state to chaotic is discovered by the cascades of period doubling bi furcation and the cascades of periodic orbit in V I phase space. Accordingl y, it is validated that change of values of the circuit parameters may lead DC DC converter to chaotic motion. Performances of the output ripples fro m steady state to chaotic are analyzed in time and frequency domains respective ly. Some important conclusions are helpful for opt imization design of DC DC converter.展开更多
An integrated 3.3V/1.2V SC DC-DC converter operating under 10MHz with a fixed duty radio of 0.5 is presented.To improve the output current of the converter,CMOS technology is adopted to fabricate the switching devices...An integrated 3.3V/1.2V SC DC-DC converter operating under 10MHz with a fixed duty radio of 0.5 is presented.To improve the output current of the converter,CMOS technology is adopted to fabricate the switching devices,and mutually compensatory circuitry technology is also employed to double the output current furthermore.The simulation results using Hspice simulation software,show that the output currents of a single unit circuit and two unit circuits connected in a mutually compensatory manner of the improved converter is about 12.5mA and 26mA,respectively.The power conversion efficiency of the mutually compensatory circuit can amount to 73%,while its output voltage ripple is less than 1.5%.The converter is fabricated in standard Rohm 0.35μm CMOS technology in Tokyo University of Japan.The test result indicates that the output current of 9.8mA can be obtained from a single unit circuit of the improved converter.展开更多
We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital c...We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital controller, the proposed DPWM can not only offer temperature/process-independent pulse widths, but also operate at a much higher clock frequency than the existing delay-line/counter DPWM structure. Post-simulation results show that with our DPWM, the system clock frequency reaches 156.9MHz while the worst variation,in a temperature range of 0 to 100℃under all process corners,is only± 9.4%.展开更多
The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）,...The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.展开更多
Two TFs （transfer functions） are needed to analyze switching DC-DC converters in control-voltage mode： the duty-cycle to output-voltage （control to output） and the input-voltage to output-voltage （line to output...Two TFs （transfer functions） are needed to analyze switching DC-DC converters in control-voltage mode： the duty-cycle to output-voltage （control to output） and the input-voltage to output-voltage （line to output）. To obtain these TFs a small-signal analysis is required. The CCM （continuous conduction mode） and the DCM （discontinuous conduction mode） analysis are different. When a circuit includes the loss resistances of the components, the number of parameters increases considerably, making manual nodal-loop circuit analysis techniques impractical to obtain the TFs. Moreover, these circuits are bilinear （non-linear） and it is necessary to linearize the equations at a DC operating-point （approximate linearization）. Vorp6rian describes a PWM （pulse-width-modulated） switch model that includes all non-linear parts of the DC-DC switching converters. This model can be linearized and replaced on the switching converter schematic leading to a linear circuit. At this point it is possible to use symbolic analysis programs to obtain these TFs or to simply apply numerical values for either the Bode diagrams or the calculation of poles and zeros. Here we describe an application of Ekrem Cangeici＇s method on X DC-DC converter to obtain control to output and line to output TFs in CCM and DCM including loss resistances. The method presented in this paper is optimized to use in the online publishing platform OctaveRS. Also the control to output TF for PCC （peak current controlled） in CCM is obtained.展开更多
The MPPT （maximum power point tracking） is one of the most important features of a regulator system that processes the energy produced by a photovoltaic generator. It is necessary, in fact, to design a controller th...The MPPT （maximum power point tracking） is one of the most important features of a regulator system that processes the energy produced by a photovoltaic generator. It is necessary, in fact, to design a controller that is able to set the output value of the voltage and ensure the working within the maximum power point. In this paper, we propose the application of the robust sliding mode control technique to a DC-DC buck converter which is combined with a classical P ＆ O （perturbation and observation） algorithm to enhance the solar system efficiency. Dynamic equations describing the boost converter are derived and a sliding mode controller for a buck converter is designed. It is shown that, this control approach gives good results in terms of robustness toward load and input voltage variations. The effectiveness of the proposed work is verified by the simulation results under PowerSim environment.展开更多
A novel high step-down non-isolated DC-DC converter has been proposed. The proposed converter consists of highly efficient non-isolated cell converters using bidirectional semiconductor power devices, and these cell c...A novel high step-down non-isolated DC-DC converter has been proposed. The proposed converter consists of highly efficient non-isolated cell converters using bidirectional semiconductor power devices, and these cell converters are connected in ISOP （input series and output parallel）. The non-isolated ISOP converter achieves high step-down ratio of D/N, operating N cell converters under the duty ratio olD. Availability of the proposed converter has been shown by developing the 48 V-12 V laboratory prototype using two 24 V-12 V cell converters. Design consideration for the 48 V-3 V multicellular converter using four 12 V-3 V cell converters has been also conducted, and the potential to approach the efficiency of 97% has been discussed. The proposed topology is suitable for the POL （point of load） converters in the highly efficient next generation DC distribution system for data centers.展开更多
A suitable inductor modeling for power electronic DC-DC converters is presented in this paper. It is developed with the aim of improving inductor losses estimation achievable by averaged models, which inherently negle...A suitable inductor modeling for power electronic DC-DC converters is presented in this paper. It is developed with the aim of improving inductor losses estimation achievable by averaged models, which inherently neglect inductor current ripple. In order to account for its contribution to the overall inductor losses, an appropriate parallel resistance is thus enclosed into the inductor model, whose value should be chosen in accordance with the DC-DC converter operating conditions. This allows the development of improved averaged models of DC-DC converters, especially in terms of power losses estimation. The effectiveness of the proposed modeling approach has been validated through a simulation study, which refers to the case of a boost DC-DC converter and is performed by means of a suitable circuit simulator designed for rapid modelling of switching power systems （SIMetrix/SIMPLIS）.展开更多
Selective harmonic elimination(SHE) in multilevel inverters is an intricate optimization problem that involves a set of nonlinear transcendental equations which have multiple local minima. A new advanced objective fun...Selective harmonic elimination(SHE) in multilevel inverters is an intricate optimization problem that involves a set of nonlinear transcendental equations which have multiple local minima. A new advanced objective function with proper weighting is proposed and also its efficiency is compared with the objective function which is more similar to the proposed one. To enhance the ability of the SHE in eliminating high number of selected harmonics, at each level of the output voltage, one slot is created. The SHE problem is solved by imperialist competitive algorithm(ICA). The conventional SHE methods cannot eliminate the selected harmonics and satisfy the fundamental component in some ranges of modulation indexes. So, to surmount the SHE defect, a DC-DC converter is applied. Theoretical results are substantiated by simulations and experimental results for a 9-level multilevel inverter. The obtained results illustrate that the proposed method successfully minimizes a large number of identified harmonics which consequences very low total harmonic distortion of output voltage.展开更多
文摘The conventional inverters have the shortcomings of straightway conduction in transistors and the difficulty of realizing soft swit￣ching. A novel inverter based on the DC/DC converter topology is presented. The inverter is comprised of a combined Buck/Boost DC/DC converter and a bridge circuit. The front stage converter is controlled to output variable DC voltage and the bridge circuit is used to convert the DC voltage to AC output. The energy feedback technology and one circle control scheme are used t...
文摘A DC DC buck converter c on trolled by naturally sampled, constant frequency PWM is considered. The existe nce of chaotic solutions and the output performance of the system under differen t circuit parameters are studied. The transforming pattern of system behavior fr om steady state to chaotic is discovered by the cascades of period doubling bi furcation and the cascades of periodic orbit in V I phase space. Accordingl y, it is validated that change of values of the circuit parameters may lead DC DC converter to chaotic motion. Performances of the output ripples fro m steady state to chaotic are analyzed in time and frequency domains respective ly. Some important conclusions are helpful for opt imization design of DC DC converter.
文摘An integrated 3.3V/1.2V SC DC-DC converter operating under 10MHz with a fixed duty radio of 0.5 is presented.To improve the output current of the converter,CMOS technology is adopted to fabricate the switching devices,and mutually compensatory circuitry technology is also employed to double the output current furthermore.The simulation results using Hspice simulation software,show that the output currents of a single unit circuit and two unit circuits connected in a mutually compensatory manner of the improved converter is about 12.5mA and 26mA,respectively.The power conversion efficiency of the mutually compensatory circuit can amount to 73%,while its output voltage ripple is less than 1.5%.The converter is fabricated in standard Rohm 0.35μm CMOS technology in Tokyo University of Japan.The test result indicates that the output current of 9.8mA can be obtained from a single unit circuit of the improved converter.
文摘We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital controller, the proposed DPWM can not only offer temperature/process-independent pulse widths, but also operate at a much higher clock frequency than the existing delay-line/counter DPWM structure. Post-simulation results show that with our DPWM, the system clock frequency reaches 156.9MHz while the worst variation,in a temperature range of 0 to 100℃under all process corners,is only± 9.4%.
基金supported by the Second Stage of Brain Korea 21 Projectsfinancially supported by Changwon National University in 2011-2013
文摘The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.
文摘Two TFs （transfer functions） are needed to analyze switching DC-DC converters in control-voltage mode： the duty-cycle to output-voltage （control to output） and the input-voltage to output-voltage （line to output）. To obtain these TFs a small-signal analysis is required. The CCM （continuous conduction mode） and the DCM （discontinuous conduction mode） analysis are different. When a circuit includes the loss resistances of the components, the number of parameters increases considerably, making manual nodal-loop circuit analysis techniques impractical to obtain the TFs. Moreover, these circuits are bilinear （non-linear） and it is necessary to linearize the equations at a DC operating-point （approximate linearization）. Vorp6rian describes a PWM （pulse-width-modulated） switch model that includes all non-linear parts of the DC-DC switching converters. This model can be linearized and replaced on the switching converter schematic leading to a linear circuit. At this point it is possible to use symbolic analysis programs to obtain these TFs or to simply apply numerical values for either the Bode diagrams or the calculation of poles and zeros. Here we describe an application of Ekrem Cangeici＇s method on X DC-DC converter to obtain control to output and line to output TFs in CCM and DCM including loss resistances. The method presented in this paper is optimized to use in the online publishing platform OctaveRS. Also the control to output TF for PCC （peak current controlled） in CCM is obtained.
文摘The MPPT （maximum power point tracking） is one of the most important features of a regulator system that processes the energy produced by a photovoltaic generator. It is necessary, in fact, to design a controller that is able to set the output value of the voltage and ensure the working within the maximum power point. In this paper, we propose the application of the robust sliding mode control technique to a DC-DC buck converter which is combined with a classical P ＆ O （perturbation and observation） algorithm to enhance the solar system efficiency. Dynamic equations describing the boost converter are derived and a sliding mode controller for a buck converter is designed. It is shown that, this control approach gives good results in terms of robustness toward load and input voltage variations. The effectiveness of the proposed work is verified by the simulation results under PowerSim environment.
文摘A novel high step-down non-isolated DC-DC converter has been proposed. The proposed converter consists of highly efficient non-isolated cell converters using bidirectional semiconductor power devices, and these cell converters are connected in ISOP （input series and output parallel）. The non-isolated ISOP converter achieves high step-down ratio of D/N, operating N cell converters under the duty ratio olD. Availability of the proposed converter has been shown by developing the 48 V-12 V laboratory prototype using two 24 V-12 V cell converters. Design consideration for the 48 V-3 V multicellular converter using four 12 V-3 V cell converters has been also conducted, and the potential to approach the efficiency of 97% has been discussed. The proposed topology is suitable for the POL （point of load） converters in the highly efficient next generation DC distribution system for data centers.
文摘A suitable inductor modeling for power electronic DC-DC converters is presented in this paper. It is developed with the aim of improving inductor losses estimation achievable by averaged models, which inherently neglect inductor current ripple. In order to account for its contribution to the overall inductor losses, an appropriate parallel resistance is thus enclosed into the inductor model, whose value should be chosen in accordance with the DC-DC converter operating conditions. This allows the development of improved averaged models of DC-DC converters, especially in terms of power losses estimation. The effectiveness of the proposed modeling approach has been validated through a simulation study, which refers to the case of a boost DC-DC converter and is performed by means of a suitable circuit simulator designed for rapid modelling of switching power systems （SIMetrix/SIMPLIS）.
文摘Selective harmonic elimination(SHE) in multilevel inverters is an intricate optimization problem that involves a set of nonlinear transcendental equations which have multiple local minima. A new advanced objective function with proper weighting is proposed and also its efficiency is compared with the objective function which is more similar to the proposed one. To enhance the ability of the SHE in eliminating high number of selected harmonics, at each level of the output voltage, one slot is created. The SHE problem is solved by imperialist competitive algorithm(ICA). The conventional SHE methods cannot eliminate the selected harmonics and satisfy the fundamental component in some ranges of modulation indexes. So, to surmount the SHE defect, a DC-DC converter is applied. Theoretical results are substantiated by simulations and experimental results for a 9-level multilevel inverter. The obtained results illustrate that the proposed method successfully minimizes a large number of identified harmonics which consequences very low total harmonic distortion of output voltage.
