电力系统的自动发电控制(automaticgeneration control,AGC)是典型的采样控制系统,具有调节周期长、通信延迟显著的特点。基于单区域负荷频率控制(load frequency control,LFC)系统,该文提出一种适用于考虑AGC采样保持特性的时滞电力系...电力系统的自动发电控制(automaticgeneration control,AGC)是典型的采样控制系统,具有调节周期长、通信延迟显著的特点。基于单区域负荷频率控制(load frequency control,LFC)系统,该文提出一种适用于考虑AGC采样保持特性的时滞电力系统频率稳定性分析方法。首先利用零阶保持器建立考虑AGC采样保持特性的LFC连续–采样混合系统模型;然后利用切比雪夫离散化方法处理模型中的时滞变量,基于函数空间方法建立等值的离散化系统;随后提出基于离散化系统特征值的稳定性判据。为说明考虑AGC采样保持特性的必要性,该文还建立了忽略AGC采样保持特性和用零阶保持器连续传递函数建模的LFC连续系统模型,通过比较不同模型的时滞稳定裕度说明不同建模方法的保守冒进程度。最后通过时滞稳定裕度上的时频域仿真分析验证所提稳定性分析方法的准确性。展开更多
A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differe...A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.展开更多
It is well-known that such non-conventional digital control schemes,such as generalized sampled-data hold functions,have clear advantages over the conventional single-rate digital control systems.However,they have the...It is well-known that such non-conventional digital control schemes,such as generalized sampled-data hold functions,have clear advantages over the conventional single-rate digital control systems.However,they have theoretical negative aspects that deviation of the input can lead to intersample oscillations or intersample ripples.This paper investigates the zero dynamics of sampleddata models,as the sampling period tends to zero,composed of a new generalized hold polynomial function,a nonlinear continuous-time plant and a sampler in cascade.For a new design of generalized hold circuit,the authors give the approximate expression of the resulting sampled-data systems as power series with respect to a sampling period up to the some order term on the basis of the normal form representation for the nonlinear continuous-time systems,and remarkable improvements in the stability properties of discrete system zero dynamics may be achieved by using proper adj us tment.Of particular interest are the stability conditions of sampling zero dynamics in the case of a new hold proposed.Also,an insightful interpretation of the obtained sampled-data models can be made in terms of minimal intersample ripple by design,where the ordinary multirate sampled systems have a poor intersample behavior.It has shown that the intersample behavior arising from the multirate input polynomial function can be localised by appropriately selecting the design parameters based on the stability condition of the sampling zero dynamics.The results presen ted here generalize the well-known notion of sampling zero dynamics from the linear case to nonlinear systems.展开更多
A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-a...A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.展开更多
文摘电力系统的自动发电控制(automaticgeneration control,AGC)是典型的采样控制系统,具有调节周期长、通信延迟显著的特点。基于单区域负荷频率控制(load frequency control,LFC)系统,该文提出一种适用于考虑AGC采样保持特性的时滞电力系统频率稳定性分析方法。首先利用零阶保持器建立考虑AGC采样保持特性的LFC连续–采样混合系统模型;然后利用切比雪夫离散化方法处理模型中的时滞变量,基于函数空间方法建立等值的离散化系统;随后提出基于离散化系统特征值的稳定性判据。为说明考虑AGC采样保持特性的必要性,该文还建立了忽略AGC采样保持特性和用零阶保持器连续传递函数建模的LFC连续系统模型,通过比较不同模型的时滞稳定裕度说明不同建模方法的保守冒进程度。最后通过时滞稳定裕度上的时频域仿真分析验证所提稳定性分析方法的准确性。
基金supported by the National Science and Technology Major Project of China(No.2012ZX03004008)
文摘A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.
基金supported by the National Natural Science Foundation of China under Grant No.61763004the Joint Funds of the Natural Science Foundation Project of Guizhou under Grant No.LH[2014]7362the Ph.D Launch Scientific Research Projects of Guizhou Institute Technology under Grant No.2014
文摘It is well-known that such non-conventional digital control schemes,such as generalized sampled-data hold functions,have clear advantages over the conventional single-rate digital control systems.However,they have theoretical negative aspects that deviation of the input can lead to intersample oscillations or intersample ripples.This paper investigates the zero dynamics of sampleddata models,as the sampling period tends to zero,composed of a new generalized hold polynomial function,a nonlinear continuous-time plant and a sampler in cascade.For a new design of generalized hold circuit,the authors give the approximate expression of the resulting sampled-data systems as power series with respect to a sampling period up to the some order term on the basis of the normal form representation for the nonlinear continuous-time systems,and remarkable improvements in the stability properties of discrete system zero dynamics may be achieved by using proper adj us tment.Of particular interest are the stability conditions of sampling zero dynamics in the case of a new hold proposed.Also,an insightful interpretation of the obtained sampled-data models can be made in terms of minimal intersample ripple by design,where the ordinary multirate sampled systems have a poor intersample behavior.It has shown that the intersample behavior arising from the multirate input polynomial function can be localised by appropriately selecting the design parameters based on the stability condition of the sampling zero dynamics.The results presen ted here generalize the well-known notion of sampling zero dynamics from the linear case to nonlinear systems.
基金supported by the National High Technology Research and Development Program of China(No.2002AA1Z1200)
文摘A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.
