A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Simulation and Design Optimization of Novel Microelectromechanical Digital-to-Analog Converter

A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Design of low-power high-frequency digital controlled DC-DC switching power converter

This paper models a low-power high-frequency digitally controlled synchronous rectifier （SR） OUCK converter. The converter is a hybrid system with three operation modes. Digital PID controler is used. Key problems such as quantization resolution of digital pulse-width modulation （DPWM） and steady-state limit cycles of digital control switching model power supply （SMPS） are discussed, with corresponding solutions presented. Simulation of a digital control synchronous buck is performed with a fixed-point algorithm. The results show that the described approach enables high-speed dynamic performance.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

Design of Digital to Analog Converters with Arbitrary Radix

There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

Digital Control Technologies for DC/DC Switching Converters

An overview of recent advances in digital control of low-to medium-power DC/DC switching converters is presented.Traditionally,analog electronics methods have dominated in controlling such DC/DC converters.However,with the steadily decreasing cost of ICs,the feasibility of digitally controlled DC/DC switching converters has increased sig-nificantly.This paper outlines a sample of digital solutions for DC/DC switching converters to enhance the performance of DC/DC switching converters.Furthermore,latest research activities pertaining to applications for steady-state and dy-namic performance improvement,such as efficiency optimization,controller auto tuning,and capacitor charge balance control,is discussed.These applications demonstrate the significant advantages and potentials of digital control.

Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.

Performance Evaluation of Wavelength Division Multiplexing Photonic Analogue-to-Digital Converters for High-Resolution Radar Systems

The performance of the wavelength division multiplexing (WDM) photonic analogue-to-digital converter (ADC) used for digitization of high-resolution radar systems is evaluated numerically by using the peak signal-to-noise ratio (SNR) metric. Two different WDM photonic ADC architectures are considered for the digitization of radar signals with 5 GHz of bandwidth (spatial resolution of 3 cm), in order to provide a comprehensive study of the compromises present when deploying radar signals with high-resolution: 1) a four-channel architecture with each channel employing an ADC with 5 GSamples/s, and 2) an eight-channel architecture with each channel employing an ADC with 2.5 GSamples/s. For peak powers of the pulsed source between 10 and 20 dBm and a distance between the radar antenna and the sensing object of 2.4 meters, peak SNR levels between 29 and 39 dB are achieved with the eight-channel architecture, which shows higher peak SNR levels when compared with the four-channel architecture. For the eight-channel architecture and for the same peak powers of the pulsed source, peak SNR levels between 11 and 16 dB are obtained when the distance increases to 13.5 meters. With this evaluation using the peak SNR, it is possible to assess the performance limits when choosing a specific radar range, while keeping the same resolution.

PULSE SHRINKING TIME-TO-DIGITAL CONVERTER FOR UWB APPLICATION

A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.

Solar Energy System with Digital Controller for Grid Connected Systems

--The solar photovoltaic （PV） module output voltage changes according to the variation of light intensity and temperature. This paper presents the implementation of an automatic digital controller of a DC-DC boost converter without batteries for a solar cell module by using a peripheral interface controller, which forms a closed loop, to control the ON-OFF period of the switching pulse. The output of DC-DC converter is maintained by automatically increasing or decreasing the pulse width. To produce the pulse width modulation （PWM）, the microcontroller is programmed according to the required duty cycle for the power switch. The PWM ON period is increased with the decrease in the PV voltage and vice-versa. The input voltage to the inverter is maintained constantly and is converted into an AC signal by using the metal-oxide-semiconductor field effect transistor （MOSFET） H-bridge operated in the sinusoidal pulse width modulation mode by using a PIC （peripheral interface controller） microcontroller. The generated AC signal can be connected to the AC grid or to the AC load. The simulated results by using Proteus 8 and hardware implemented results verify the effectiveness of the proposed controller.

ADC border effect and suppression of quantization error in the digital dynamic measurement

The digital measurement and processing is an important direction in the measurement and control field. The quantization error widely existing in the digital processing is always the decisive factor that restricts the development and applications of the digital technology. In this paper, we find that the stability of the digital quantization system is obviously better than the quantization resolution. The application of a border effect in the digital quantization can greatly improve the accuracy of digital processing. Its effective precision has nothing to do with the number of quantization bits, which is only related to the stability of the quantization system. The high precision measurement results obtained in the low level quantization system with high sampling rate have an important application value for the progress in the digital measurement and processing field.

Design and Implementation of a Cueing Wideband Digital EW Receiver

A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.

Efficient structures for wideband digital receiver

Digital receivers have become more and more popular in radar, communication, and electric warfare for the advantages compared with their analog counterparts. But conventional digital receivers have been generally considered impractical for bandwidth greater than several hundreds MHz. To extend receiver bandwidth, decrease data rate and save hardware resources, three novel structures are proposed. They decimate the data stream prior to mixing and filtering, then process the multiple decimated streams in parallel at a lower rate. Consequently it is feasible to realize wideband receivers on the current ASIC devices. A design example and corresponding simulation results are demonstrated to evaluate the proposed structures.

A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.

An in situ Digital Background Calibration Algorithm for Multi-Channel R-βR Ladder DACs

The R-2R resistor ladder is one of the best topologies for implementing compact-sized digital-to-analog converter(DAC)arrays in implantable neuro-stimulators.However,it has a limited resolution and considerable inter-channel variation due to component mismatches.To avoid losing analog information,we present sub-radix-2 DAC implemented by the R-βR resistor ladder in this paper.The digital successive approximation register(DSAR)algorithm corrects the transfer function of DACs based on their actual bit weights.Furthermore,a low-cost in situ adaptive bit-weight calibration(ABC)algorithm drives the analog output error between two DACs to zero by adjusting their bit weights automatically.The simulation results show that the proposed algorithm can calibrate the non-linear transfer function of each DAC and the gain error among multiple channels in the background.