A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC...A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.展开更多
The m series with 511 bits is taken as an example being applied in non-coherent integra- tion algorithm. A method to choose the bi-phase code is presented, which is 15 kinds of codes are picked out of 511 kinds of m s...The m series with 511 bits is taken as an example being applied in non-coherent integra- tion algorithm. A method to choose the bi-phase code is presented, which is 15 kinds of codes are picked out of 511 kinds of m series to do non-coherent integration. It is indicated that the power in- creasing times of larger target sidelobe is less than the power increasing times of smaller target main- lobe because of the larger target＇ s pseudo-randomness. Smaller target is integrated from larger tar- get sidelobe, which strengthens the detection capability of radar for smaller targets. According to the sidelobes distributing characteristic, a method is presented in this paper to remove the estimated sidelobes mean value for signal detection after non-coherent integration. Simulation results present that the SNR of small target can be improved approximately 6. 5 dB by the proposed method.展开更多
DDS(直接数字频率合成,direct digital frequency synthesis)是一种全数字化设计信号发生器的方法。基于PSOC(programming system on chip)芯片技术,以Creator集成环境作为设计开发平台,实现DDS信号发生器各个模块的功能。根据DDS的结...DDS(直接数字频率合成,direct digital frequency synthesis)是一种全数字化设计信号发生器的方法。基于PSOC(programming system on chip)芯片技术,以Creator集成环境作为设计开发平台,实现DDS信号发生器各个模块的功能。根据DDS的结构和原理,推导得到参考频率与输出频率间的关系。利用Creator提供的固件元件,给出了元件的属性配置和使用方法。该设计充分体现了PSOC集成度高,图形化编程在嵌入式系统设计中的优势。展开更多
基金Supported by the Ministerial Level Advanced Research Foundation (SP240012)
文摘A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.
基金Supported by the National Natural Science Foundation of China(Youth Science Fund)(61001190)
文摘The m series with 511 bits is taken as an example being applied in non-coherent integra- tion algorithm. A method to choose the bi-phase code is presented, which is 15 kinds of codes are picked out of 511 kinds of m series to do non-coherent integration. It is indicated that the power in- creasing times of larger target sidelobe is less than the power increasing times of smaller target main- lobe because of the larger target＇ s pseudo-randomness. Smaller target is integrated from larger tar- get sidelobe, which strengthens the detection capability of radar for smaller targets. According to the sidelobes distributing characteristic, a method is presented in this paper to remove the estimated sidelobes mean value for signal detection after non-coherent integration. Simulation results present that the SNR of small target can be improved approximately 6. 5 dB by the proposed method.
文摘DDS(直接数字频率合成,direct digital frequency synthesis)是一种全数字化设计信号发生器的方法。基于PSOC(programming system on chip)芯片技术,以Creator集成环境作为设计开发平台,实现DDS信号发生器各个模块的功能。根据DDS的结构和原理,推导得到参考频率与输出频率间的关系。利用Creator提供的固件元件,给出了元件的属性配置和使用方法。该设计充分体现了PSOC集成度高,图形化编程在嵌入式系统设计中的优势。
