Towards integrated mode-division demultiplexing spectrometer by deep learning

Miniaturized spectrometers have been widely researched in recent years,but few studies are conducted with on-chip multimode schemes for mode-division multiplexing(MDM)systems.Here we propose an ultracompact mode-division demultiplexing spectrometer that includes branched waveguide structures and graphene-based photodetectors,which realizes simultaneously spectral dispersing and light fields detecting.In the bandwidth of 1500-1600 nm,the designed spectrometer achieves the single-mode spectral resolution of 7 nm for each mode of TE_(1)-TE_(4) by Tikhonov regularization optimization.Empowered by deep learning algorithms,the 15-nm resolution of parallel reconstruction for TE_(1)-TE_(4) is achieved by a single-shot measurement.Moreover,by stacking the multimode response in TE_(1)-TE_(4) to the single spectra,the 3-nm spectral resolution is realized.This design reveals an effective solution for on-chip MDM spectroscopy,and may find applications in multimode sensing,interconnecting and processing.

Compact and high-efficient wavelength demultiplexing coupler based on high-index dielectric nanoantennas

Wavelength demultiplexing waveguide couplers have important applications in integrated nanophotonic devices. Two of the most important indicators of the quality of a wavelength demultiplexing coupler are coupling efficiency and splitting ratio. In this study, we utilize two asymmetric high-index dielectric nanoantennas directly positioned on top of a silicon-on insulator waveguide to realize a compact wavelength demultiplexing coupler in a communication band, which is based on the interference of the waveguide modes coupled by the two nanoantennas. We add a Au substrate for further increasing the coupling efficiency. This has constructive and destructive influences on the antenna＇s in-coupling efficiency owing to the Fabry-Perot（FP） resonance in the SiO2 layer. Therefore, we can realize a wavelength demultiplexing coupler with compact size and high coupling efficiency. This coupler has widespread applications in the areas of wavelength filters,on-chip signal processing, and integrated nanophotonic circuits.

Mode demultiplexing hybrids for mode-division multiplexing coherent receivers

We propose a mode demultiplexing hybrid(MDH) that integrates mode demultiplexing, local oscillator power splitting, and optical 90-deg mixing using multi-plane light conversion(MPLC). We demonstrate the realization of a three-mode MDH using four phase plates, one more than what is required for an MPLC-based mode demultiplexer, via numerical simulations. The performance of the three-mode MDH is comparable to that of commercial single-mode 90-deg hybrids. This multiple-functionality device enables simplification of the coherent optical front end of mode-division multiplexing receivers.

Coupling length variation and multi-wavelength demultiplexing in photonic crystal waveguides

In this Letter, the effects of material/structure parameters of photonic crystal（Ph C） parallel waveguides on the coupling length are investigated. The results show that, increasing the effective relative permittivity of the Ph C leads to a downward shift of the photonic bandgap and a variation of the coupling length. A compact Ph C 1.31/1.55 μm wavelength division multiplexer（WDM）/demultiplexer with simple structure is proposed,where the output power ratios are more than 24 d B. This WDM can multiplex/demultiplex other light waves efficiently.

Simultaneous clock recovery and demultiplexing of a 320 Gb/s OTDM system using an optoelectronic oscillator based on cascaded MZM and PolM

An improved optoelectronic oscillator scheme for an optical time division multiplexing （OTDM） system based on cascaded Mach-Zehnder modulator （MZM） and polarization modulator （PolM） is experimentally investigated. The system can simultaneously realize clock recovery and demultiplexing. With the MZM working at peak point to generate return-to-zero-33 optical pulses and the PolM working as an equivalent intensity modulator, a high-quality clock signal with 35-fs timing jitter is extracted from the 160-GBaud OTDM-differential quaternary phase-shift keying signal. Narrow short optical switch gates （4 ps） are also generated to demultiplex 160-GBaud signals to 40-GBaud signals. Error-free performance is achieved with 2.4-dB power penalty in the worst case.

A novel successive demultiplexing scheme based on optical-CDMA balanced demodulation for FBG sensor systems

In order to increase the multiplexing density of the fiber Bragg gratings （FBGs） for a low cost per-sensor, based on the analysis of the spectrum shadow distortion （SSD）, a novel successive demultiplexing scheme for FBG sensors has been developed. It is based on the optical cade division multiple access （CDMA） balanced demodulation. A high-density multiplexing-demultiplexing system for FBG sensors has been designed, and corresponding simulation carried out has demonstrated that the FBG sensors＇ reflective signals can still be obtained accurately and respectively, even if FBG sensors＇ operating bandwidths heavily overlap. The SSD has been greatly mitigated.

40-to-10-Gb/s demultiplexing using an electro-absorption sampling window

The demultiplexing experiment from a 40 Gb/s optical time-division multiplexing signal is completed by using electro- absorption sampling window based on electronic phase-locked loop circuit for clock recovery. Error-free demultiplexing is achieved when the launched optical power into electro-absorption sampling window reaches 5.5 dBm without optical filter following the EDFA.

Wavelength division demultiplexing by photonic crystal waveguides with asymmetric corrugated surfaces

We propose a new type of wavelength division demultiplexer composed of a photonic crystal waveguide with asymmetric corrugated exit surface. The focus displacement for different symmetric corrugated surfaces is relative to the intensity of the excited surface mode. By systematically investigating the effects of the parameters of the corrugated surface on the focus shift, we demonstrate an on-axis focus by a photonic crystal waveguide with an asymmetric corrugated exit surface at a specific wavelength. The precise equivalences of surface modes at each side of the exit surface are broken. Thus, for the light source with other wavelengths, the emerging beams are off-axis focused at different directions, similar to the function of a wavelength division demultiplexer.

Flexible polarization demultiplexing method based on an adaptive process noise covariance Kalman filter

A flexible polarization demultiplexing method based on an adaptive Kalman filter（AKF） is proposed in which the process noise covariance has been estimated adaptively. The proposed method may significantly improve the adaptive capability of an extended Kalman filter（EKF） by adaptively estimating the unknown process noise covariance. Compared to the conventional EKF, the proposed method can avoid the tedious and time consuming parameter-by-parameter tuning operations. The effectiveness of this method is confirmed experimentally in 128 Gb/s 16 QAM polarization-division-multiplexing（PDM） coherent optical transmission systems. The results illustrate that our proposed AKF has a better tracking accuracy and a faster convergence（about 4 times quicker）compared to a conventional algorithm with optimal process noise covariance.

Half baudrate electrical clock based demultiplexing scheme for OTDM-DQPSK signal using SOA and optical filter

A demultiplexing scheme based on semiconductor optical amplifier（SOA）and optical filter for optical time division multiplexing differential quadrature phase shift keying（OTDM-DQPSK）system is proposed and investigated experimentally.With only a common half baudrate electrical clock modulated 33%duty cycle return-to-zero（RZ-33）optical clock signal as pump,this scheme is cost-effective,energy-efficient,and integration-potential.A proof-of-concept experiment is carried out for the demultiplexing of a 2×40-GBd OTDM-DQPSK signal.Error-free performance is demonstrated,and the average power penalty for both channels is about 3 dB.

New Structure for Multi-Channel Demultiplexing

A new all optical demultiplexer based on nonlinear effect in semiconductor laser amplifier (SLA) is proposed. It can demultiplex all channels of the OTDM signal concurrently, and it can also be integrated on a single chip. The proposed device consists of a series short Fabry Perot amplifiers (FPSLA) setting on the path vertically, through which the preamplified optical signal travels. Perpendicularly to the signal, K(channel number) paralleled beams of light pulse, which act as probes with repetition at the bit rate of one channel, irradiate on these FP SLAs , respectively, just when the corresponding signal channel pulse passes through the active region from lateral side. The transmissivity depends on the signal pulse. Theoretical analysis has been given. As a demonstrating example, a device operated at the speed of 25Gbit/s (2.5Gbit/s×10 ) is simulated and the results show that the about 9.24 dB extinction ratio can be achieved easily.

2.5Gb/s Monolithic IC of Clock Recovery,Data Decision,and 1∶4 Demultiplexer

A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.

20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS

A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET logic structure latch, its power supply voltage is lower and the speed is faster. In addition, the negative feedback is used in the buffer circuit to widen its bandwidth. Measurement results show that the chip can work at the data rate of 20Gb/ s. The supply voltage is 1.8V and the current,including the buffer circuit, is 72mA.

Symbols detection for frequency-selective V-BLAST OFDM systems

As the combining form of the orthogonal frequency-division multiplexing (OFDM) technique and the vertical Bell Labs layered space-time (V-BLAST) architecture, the V-BLAST OFDM system can better meet the demand of next-generation (NextG) broadband mobile wireless multimedia communications. The symbols detection problem of the V-BLAST OFDM system is investigated under the frequency-selective fading environment. The joint space-frequency demultiplexing operation is proposed in the V-BLAST OFDM system. Successively, one novel half-rate rotational invariance joint space-frequency coding scheme for the V-BLAST OFDM system is proposed. By elegantly exploiting the above rotational invariance property, we derive one direct symbols detection scheme without knowing channels state information (CSI) for the frequency-selective V-BLAST OFDM system. Extensive simulation results demonstrate the validity of the novel half-rate rotational invariance joint space-frequency coding scheme and the performance of the direct symbols detection scheme.

8×2.5Gb/s 100km OTDM Experiment System

An 8×2.5Gb/s 100km optical time division multiplexing(OTDM) experiment system is reported, which employs an electrical filter with high Q value for clock extraction, a nonlinear optical loop mirror(NOLM) for demultiplering and chirped fiber grating for dispersion compensation. The error free operation is achieved and the experiment results are given.

Optimization of Diffraction Efficiency and Polarization Dependence Loss in Photopolymer Grating for Use in Multichip Module

We in this paper propose a model to increase the diffraction efficiency of a holographic grating at 1550 nm for multiplexing application. To use such a grating, polarization dependence loss is introduced analytically and then optimized for its minimum value A configuration of holographic grating is proposed based on both maximum diffraction efficiency and minimum polarization dependence loss. The proposed grating is expected to find importance in optoelectronic multichip module.

A kind of low-power 10 Gbit/s CMOS 1∶4 demultiplexer

A 10 Gbit/s 1：4 demultiplexer（DEMUX） fabricated in 0. 18 μm CMOS （complementary metal-oxidesemiconductor transistor） technology for optical-fiber-link is presented. The system is constructed in tree-type structure and it includes a high-speed 1 ： 2 DEMUX, two low-speed 1 ： 2 DEMUXs, a divider, and input and output buffers for data and dock. To improve the circuit performance and reduce the power consumption, a latch structure with a common-gate topology and a single clock phase is employed in the high-speed 1 ： 2 DEMUX and the 5 GHz 1 ： 2 on-chip frequency divider, while dynamic CMOS logic is adopted in the low-speed l ： 2 DEMUXs. Measured results at 10 Gbit/s by 23^31 -1 pseudo random bit sequences （PRBS） via on-wafer testing indicate that it can work well with a power dissipation of less than 100 mW at 1.8 V supply voltage. The die area of the DEMUX is 0. 65 mm × 0. 75 mm.

12Gb/s 0.25μm CMOS Low-Power 1∶4 Demultiplexer

A low power 12Gb/s single-stage 1 ： 4 demultiplexer （DEMUX） applied in SONET OC-192 is realized in TSMC＇s mix-signal 0. 25μm CMOS. All of the circuits are in source coupled FET logic （SCFL） to achieve as high a speed as possible and suppress common mode distortions. This DEMUX is featured for achieving singlestage demultiplexing by using a quarter-rate IQ clock. This method not only reduces the components of the DEMUX but also lowers its power dissipation. The fabricated DEMUX operates error free at 12Gb/s by 231 - 1 pseudorandom bit sequences in on-wafer testing. The chip size is 0. 9mm × 0.9mm and the power dissipation is only 210mW with a single 2.5V supply.

20 Gbit/s 1∶2 demultiplexer of low-power using 0.18 μm CMOS

A 1 ： 2 demultiplexer（DEMUX） that is fabricated using 0. 18 μm CMOS （complementary metaloxide-semiconductor transistor） technology is presented. The DEMUX consists of a master-slave-slave, masterslave D flip-flops and output buffers. The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors. The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode. In addition, the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit. Measurement results at 20 Gbit/s 2^23 - 1 pseudo random bit sequence （PRBS） via on-wafer testing show that the 1： 2 DEMUX can operate well. The power dissipation is 108 mW with the area of 475μm×578μm.

10 Gbit/s 0.25μm CMOS 1∶4 demultiplexer

A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.