In satellite mobile communication system, relative movement of the satellite and the terminal will cause a large Doppler offset. Timing advanced estimation with Zadoff-Chu sequence is sensitive to the frequency offset...In satellite mobile communication system, relative movement of the satellite and the terminal will cause a large Doppler offset. Timing advanced estimation with Zadoff-Chu sequence is sensitive to the frequency offset. When the frequency offset is larger than one times subcarrier spacing, the value of peak cannot be detected at the receiving end. To suppress the larger Doppler frequency shift, this paper proposes a novel timing advanced estimation scheme(TAE-MCD) for satellite communication system. In this algorithm, t r a n s m i t t e d s i g n a l i s d i v i d e d i n t o Z C sequence and its conjugate sequence. Using multiplication and DFT operation to find the estimated peak at the receiving end, and make subtraction with the obtained sequences at last. The scheme can not only inhibit the adverse effects of large Doppler frequency shift in timing estimation effectively, but also reduce the computational complexity at the receiving end and improve the work efficiency of the hardware. Simulations results show that TAEMCD outperform the existing timing advanced estimation methods, on the condition of no additional time and frequency resource are needed.展开更多
This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. ...This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.展开更多
基金supported by the Science and Technology on Information Transmission and Dissemination in Communication Networks Laboratory (ITD-U13007/ KX132600014)the National Natural Science Foundation of China (No. 9143810063)the Fundamental Research Funds for the Central Universities (2014RC0202)
文摘In satellite mobile communication system, relative movement of the satellite and the terminal will cause a large Doppler offset. Timing advanced estimation with Zadoff-Chu sequence is sensitive to the frequency offset. When the frequency offset is larger than one times subcarrier spacing, the value of peak cannot be detected at the receiving end. To suppress the larger Doppler frequency shift, this paper proposes a novel timing advanced estimation scheme(TAE-MCD) for satellite communication system. In this algorithm, t r a n s m i t t e d s i g n a l i s d i v i d e d i n t o Z C sequence and its conjugate sequence. Using multiplication and DFT operation to find the estimated peak at the receiving end, and make subtraction with the obtained sequences at last. The scheme can not only inhibit the adverse effects of large Doppler frequency shift in timing estimation effectively, but also reduce the computational complexity at the receiving end and improve the work efficiency of the hardware. Simulations results show that TAEMCD outperform the existing timing advanced estimation methods, on the condition of no additional time and frequency resource are needed.
文摘This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.
