The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchronization ,and the latency caused by instructions that take mult...The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchronization ,and the latency caused by instructions that take multiple cycles to produce results To tolerate these three types of latencies, The following techniques was proposed to couple: coarse-grained multithreading, the superscalar processor and a reconfigurable device, namely the overlapping long latency operations of one thread of computation with the execution of other threads The superscalar processor principle is used to tolerate instruction latency by issuing several instructions simultaneously The DPGA is coupled with this processor in order to improve the context-switching展开更多
There is an increasing interest of using the Programmable arrays for performing different hardware. In this paper we give an alternative approach and the applications of the Programmable Gate Arrays. We show the field...There is an increasing interest of using the Programmable arrays for performing different hardware. In this paper we give an alternative approach and the applications of the Programmable Gate Arrays. We show the field and the domain where they are more adequate and wihch kind of Programmable array is more efficient to apply. The DPGA and the FPGA are both Programmable Gate Array. They have more possibilities then the conventional devices such as 64 bits microprocessor, however a microprocessor coupled with a programmable array has more opportunity and their implementation is increasing. It is impossible to enumerate all possible uses of Programmable Gate Array. However we use the parameters Latency and throughput. Finite State Machine(FSM), control of data path, processor coupled with a programmable array to build up an alternative approach of the devices and their applications.展开更多
Distributed Systems (DS) have a collection of heterogeneous computing resources to process user tasks. Task scheduling in DS has become prime research case, not only due of finding an optimal schedule, but also becaus...Distributed Systems (DS) have a collection of heterogeneous computing resources to process user tasks. Task scheduling in DS has become prime research case, not only due of finding an optimal schedule, but also because of the time taken to find the optimal schedule. The users of Ds services are more attentive about time to complete their task. Several algorithms are implemented to find the optimal schedule. Evolutionary kind of algorithms is one of the best, but the time taken to find the optimal schedule is more. This paper presents a distance-based Pareto genetic algorithm (DPGA) with the Map Reduce model for scheduling independent tasks in a DS environment. In DS, most of the task scheduling problem is formulated as multi-objective optimization problem. This paper aims to develop the optimal schedules by minimizing makespan and flow time simultaneously. The algorithm is tested on a set of benchmark instances. MapReduce model is used to parallelize the execution of DPGA automatically. Experimental results show that DPGA with MapReduce model achieves a reduction in makespan, mean flow time and execution time by 12%, 14% and 13% than non-dominated sorting genetic algorithm (NSGA-II) with MapReduce model is also implemented in this paper.展开更多
文摘The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchronization ,and the latency caused by instructions that take multiple cycles to produce results To tolerate these three types of latencies, The following techniques was proposed to couple: coarse-grained multithreading, the superscalar processor and a reconfigurable device, namely the overlapping long latency operations of one thread of computation with the execution of other threads The superscalar processor principle is used to tolerate instruction latency by issuing several instructions simultaneously The DPGA is coupled with this processor in order to improve the context-switching
文摘There is an increasing interest of using the Programmable arrays for performing different hardware. In this paper we give an alternative approach and the applications of the Programmable Gate Arrays. We show the field and the domain where they are more adequate and wihch kind of Programmable array is more efficient to apply. The DPGA and the FPGA are both Programmable Gate Array. They have more possibilities then the conventional devices such as 64 bits microprocessor, however a microprocessor coupled with a programmable array has more opportunity and their implementation is increasing. It is impossible to enumerate all possible uses of Programmable Gate Array. However we use the parameters Latency and throughput. Finite State Machine(FSM), control of data path, processor coupled with a programmable array to build up an alternative approach of the devices and their applications.
文摘Distributed Systems (DS) have a collection of heterogeneous computing resources to process user tasks. Task scheduling in DS has become prime research case, not only due of finding an optimal schedule, but also because of the time taken to find the optimal schedule. The users of Ds services are more attentive about time to complete their task. Several algorithms are implemented to find the optimal schedule. Evolutionary kind of algorithms is one of the best, but the time taken to find the optimal schedule is more. This paper presents a distance-based Pareto genetic algorithm (DPGA) with the Map Reduce model for scheduling independent tasks in a DS environment. In DS, most of the task scheduling problem is formulated as multi-objective optimization problem. This paper aims to develop the optimal schedules by minimizing makespan and flow time simultaneously. The algorithm is tested on a set of benchmark instances. MapReduce model is used to parallelize the execution of DPGA automatically. Experimental results show that DPGA with MapReduce model achieves a reduction in makespan, mean flow time and execution time by 12%, 14% and 13% than non-dominated sorting genetic algorithm (NSGA-II) with MapReduce model is also implemented in this paper.
