针对局部阴影条件下光伏阵列输出效率低并且对最大功率点跟踪MPPT(Maximum Power Point Tracking)收敛速度慢的问题,设计出一种基于DSP的智能MPPT控制器。提出一种目标因子与过渡机制的改进蚁群全局寻优二阶段MPPT全局寻优算法作,引入...针对局部阴影条件下光伏阵列输出效率低并且对最大功率点跟踪MPPT(Maximum Power Point Tracking)收敛速度慢的问题,设计出一种基于DSP的智能MPPT控制器。提出一种目标因子与过渡机制的改进蚁群全局寻优二阶段MPPT全局寻优算法作,引入目标导向因子避免盲目寻优,引入过渡机制而弥补寻优末期的振荡完成最大功率跟踪。通过仿真与实验的分析表明,改进后的算法在光照突变时具有较快的响应速度和较高的跟踪精度,避免系统趋于稳定时的功率振荡,提高了系统效率。展开更多
This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Se...This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.展开更多
文摘针对局部阴影条件下光伏阵列输出效率低并且对最大功率点跟踪MPPT(Maximum Power Point Tracking)收敛速度慢的问题,设计出一种基于DSP的智能MPPT控制器。提出一种目标因子与过渡机制的改进蚁群全局寻优二阶段MPPT全局寻优算法作,引入目标导向因子避免盲目寻优,引入过渡机制而弥补寻优末期的振荡完成最大功率跟踪。通过仿真与实验的分析表明,改进后的算法在光照突变时具有较快的响应速度和较高的跟踪精度,避免系统趋于稳定时的功率振荡,提高了系统效率。
基金Supported by the National High Technology Research & Development Program of China (863 Program) (2002AA1Z1140).
文摘This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.
