基于DW8051的I^2C控制器设计

基于DW8051软核,采用Verilog语言,设计了I2C控制器,并通过SFR接口总线将I^2C控制器挂接在了DW8051上,详细介绍了I^2C协议原理和SFR总线写模块实现方法。该设计通用性强,为DW8051软核挂接不同外设提供了一套详细可行的解决方案,值得推广。

基于DW8051的SPI控制器设计

SPI总线是Motorola公司提出的一个同步串行外设,容许CPU与各种外围接口器件以串行方式进行通信。设计了一款基于DW8051用户外设总线的SPI控制器,该控制器由硬件描述语言Verilog HDL实现,可以通过在DW8051上运行的用户程序控制。该控制器具有独立的深度为16的发送和接收缓冲FIFO、功能丰富的控制寄存器以及其扩展性。设计的SPI控制器模型符合SPI通信标准,最终下载到FPGA中,通过该控制器控制一款基于SPI接口的Flash存储器验证其功能的正确性。

基于DW8051平台的MPU设计与验证

在集成电路设计中,芯片的安全性和可靠性受到了越来越多的关注和重视。实现了DW8051单片机平台上MPU即存储保护单元IP的设计与验证,采用分区权限保护的思想,可配置不同分区之间相互的读、写及执行权限,旨在为系统提供存储保护的硬件支持,为系统的存储空间提供了访问权限保护,增强了芯片的安全性。可以应用于智能IC卡、USB KEY等对存储保护有需求的嵌入式系统的芯片中。

Embedded TCP/IP Chip Based on DW8051 Core

As remote control for electric home appliances thro ug h the Internet becomes more common, many compannies today launched a new corpora te initiative to develop advanced embedded solutions for Internet connectivity t hat can be applied to a boundless number of products such as information applian ces and non-PC devices. The most representative products are CMX-MicroNet which provides true TCP/IP ca pabilities for 8-bit and 16-bit microprocessors and eZ80Internet Engine which provides easy Internet connectivity for 8-bit devices. Pushed by the extraordinary success of these products, we have developped a kin d of embedded TCP/IP chip based on DW8051 Core.With some significant features su ch as establishing several connections at a same time, low-cost and high speed, we hope it will possess its own "embedded Internet" market. There are three most common application fields of the embedded TCP/IP chip. a) connection embedded microcontroller-based devices such as electric home appl iances to Internet b) allowing the remote control and monitoring of devices in the field via the In ternet c) allowing a remote device to send messages via email to, for example, a servic e centre. The working process of communication with embedded TCP/IP chip is described as f ollows.When it starts to work, it keeps on waiting the connection request from t he host and getting the requisite information such as destination IP address,des tination port through the host interface.Then it should connect to the ISP. A di al-up modem makes the connection and then the connection is negotiated. When bo th end systems begin to communicate, the chip keeps on transmitting datagram bet ween them and inspecting every phase of the connection to ensure the communicati on. The innovation of this design is the successful usage of separate CRC module and UART module, as can improve the speed and performance of this chip greatly. Suc h kind of efficiency improvement brought by the proposed design has been proved on Altera’s SOPC(System On a Programmable Chip). The whole system has been val idated through hardware emulation platform. The core has been mapped on APEX EP2 0K400E and works under the frequency of 25 MHZ.

基于DW8051的P1口设计及FPGA实现

为提升DW8051单片机的使用体验、简化操作流程,本文在Synopsys公司提供的DW8051单片机软核的基础上,使用Verilog编程语言设计了与外设进行数据交互的I/O(Input/Output)接口,并将该I/O接口作为DW8051的一个外设挂载到MCU核的总线上,同时,在FPGA芯片上测试实现。通过该I/O接口,标准8051单片机用户可以更加方便的使用DW8051单片机,减少不必要的学习成本,降低开发难度,提高开发效率。在Altera公司的开发板上测试数据的读入和写出操作。测试结果表明,该I/O接口能正确读入数据到单片机中,单片机也能通过该I/O口写出数据,测试结果满足预期。通过使用该I/O接口,简化了DW8051的使用难度,可满足用户的基本需要。

基于DW8051的LCD控制接口的设计与应用

DW8051是一款采用Verilog语言设计的兼容MCS-51指令集的单片机软核,可在FPGA中实现。基于DW8051,根据SFR外设控制原理,采用硬件描述语言Verilog HDL,实现了一个DW8051与LCD控制器的接口,并在EP2C70F896C6N FPGA中实现整个系统的综合、配置,外接1602液晶模块进行显示控制测试。该方法可以用于其他外设接口的设计实现,实现基于DW8051的SOPC系统。

数字对讲机基带SoC中央处理模块的设计

DW8051是兼容MCS-51指令集的8位处理器内核。介绍了基于DW8051的数字对讲机基带SoC中央处理模块的设计。分析了基带SoC的架构以及中央处理模块的职能,设计了一个验证平台检验低端的8051处理器能否满足工作要求,详细讨论了基于DW8051 IP core的中央处理模块的设计方法和验证过程。

基于FPGA的一种μC/OS-Ⅱ硬件加速器设计

为了让实时操作系统更快更确定地处理复杂任务,本文以μC/OS-II为基础,采用软、硬件协同设计的方法,通过将内核中耗时和关键性的操作转移到硬件,提高系统确定性和速度。同时,采用现场可编程门阵列(field programmable gate array,FPGA)技术,实现硬件加速器的设计,中央处理器(central processing unit,CPU)与加速器的通信,通过DW8051的特殊功能寄存器总线(special function register,SFR)实现,并利用Altera公司的DE1-SoC开发板作为验证平台进行实验。实验结果表明,任务切换效率比原μC/OS-II系统提高了446倍,节省了时钟中断处理时间,提高了μC/OS-II系统的性能。该设计具有一定的实际应用价值。