CMOS Automatic Gain Control Circuit with DC Offset Cancellation for FM/cw Ladar

This paper presented an automatic gain control(AGC) circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier(VGA) chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 μm standard CMOS process. Simulation and measurement results verified that its gain ranged from-20 dB to 30 dB, and bandwidth ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.

Power and Voltage Control Based on DC Offset Injection for Bipolar Low-voltage DC Distribution System

The bipolar low-voltage DC(LVDC) distribution system has become a prospective solution to better integration of renewables and improvement of system efficiency and reliability. However, it also faces the challenge of power and voltage imbalance between two poles. To solve this problem, an interface converter with bipolar asymmetrical operating capabilities is applied in this paper. The steady-state models of the bipolar LVDC distribution system equipped with this interface converter in the gridconnected mode and off-grid mode are analyzed. A control scheme based on DC offset injection at the secondary side of the interface converter is proposed, enabling the bipolar LVDC distribution system to realize the unbalanced power transfer between two poles in the grid-connected mode and maintain the inherentpole voltage balance in the off-grid mode. Furthermore, this paper also proposes a primary-side DC offset injection control scheme according to the analysis of the magnetic circuit model, which can eliminate the DC bias flux caused by the secondaryside DC offset. Thereby, the potential core magnetic saturation and overcurrent issues can be prevented, ensuring the safety of the interface converter and distribution system. Detailed simulations based on the proposed control scheme are conducted to validate the function of power and voltage balance under the operation conditions of different DC loads.

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA（RXPGA） provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA（TXPGA） covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA （I and Q path） under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC（DC offset cancellation） circuit shows 10 kHz of HPCF（high pass cutoff frequency） and the DCOC settling time is less than 0.45μs.

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.

A programmable gain amplifier with digitally assisted DC offset calibration for a direct-conversion WLAN receiver

This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications. The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing. The calibration loop achieves constant high-pass pole when gain changes; and a fast response time by programming the pole to 1 MHz during preamble and to 30 kHz during receiving data. The transmitter baseband employs an auto-calibration loop with on-chip AD and DA to suppress the carrier leakage, and AD can be powered down after calibration to save power consumption. The chip consumes 17.52 mA for RX baseband VGA and DCOC, and 8.3 mA for TX carrier leakage calibration （5.88 mA after calibration） from 2.85 V supply. Implemented in a 0.35μm SiGe technology, they occupy 0.68 mm^2 and 0.18 mma die size respectively.

A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

A low power mixed signal DC offset calibration （DCOC） circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 ×0.419 mm^2.

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.

DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applications

Fast and accurate monitoring of the phase,amplitude,and frequency of the grid voltage is essential for single-phase grid-connected converters.The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters.In this paper,a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation(ADSC)in a second-order generalized integrator(SOGI)phase-locked loop(PLL).A frequency-fixed SOGI-based PLL(FFSOGI-PLL)is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs.A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral(PI)controller gains.The effects of frequency variation and ADSC on the proposed PLL are considered,and correction methods are adopted to accurately estimate grid information.The simulation results are presented,along with comparisons to other single-phase PLLs in terms of settling time,peak frequency,and phase error to validate the proposed PLL.The dynamic performance of the proposed PLL is also experimentally validated.Overall,the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices,offering an improved solution for precise grid synchronization in single-phase applications.

一种100 MHz~4 GHz宽带抗干扰射频接收机的设计

为满足导航、通信、相控阵雷达以及电子对抗等领域对高性能接收终端的需求,提高系统的抗干扰、通用化和小型化性能,设计了一款工作频率在100 MHz~4 GHz的宽带抗干扰接收机芯片。接收机结构采用直接下变频形式,包括单转差巴伦、无源混频器和移相器等,能够有效抑制频带内的干扰信号,在强干扰信号下整个接收机通道不阻塞,能检测出极小的有用信号,同时保证与没有干扰状态相比性能不恶化。针对零中频(zero-Intermediate Frequency,zero-IF)接收机容易产生本振泄露、自混频等现象,设计了直流失调校准、本振相位调整等功能,可实现直流偏置点5 mV的补偿。射频输入100 MHz~4 GHz变化时,混频器转换增益≥31.2 dB。

基于二阶变增益滑模的感应电机电压模型磁链观测器

针对无速度传感器感应电机驱动系统,基于二阶滑模的电压模型磁链观测器可以有效提升传统开环电压模型观测器的转速估计鲁棒性。然而,现有二阶滑模电压模型观测器仍然存在以下2个问题:1)滑模观测器常数增益与可变稳定性条件间的不匹配问题;2)由于存在直流偏置,需要采用非理想积分器来估计转子磁链。针对这2个问题,该文提出相应解决方案:1)改进二阶滑模观测器结构,并根据稳定性条件设计可变增益,以同时实现宽调速范围内的观测器稳定性与抖振抑制;2)根据滑模观测器的输出,设计一种带直流偏置补偿的积分器,以提升磁链估计精确度。最后,在3.7 kW的感应电机实验装置上进行对比实验,证明所提方法有效性。

适用于WLAN接收机的高线性电流模式混频器设计

针对无线局域网接收机对低成本和线性度的定制化需求,设计了一款适用于IEEE 802.11 b/g/n/ax标准WLAN接收机的高线性度电流模式混频器;采用零中频接收机架构,电流模式混频器的电路结构主要包括跨导级放大器,混频开关级和跨阻放大器;通过跨导级两种工作状态的转换和跨阻放大器反馈电阻的两种取值变化实现了混频器的四档增益可调;混频开关级选用双平衡无源混频电路以提供良好的线性度;为了解决零中频接收机存在的直流失调问题,加入了一种电流注入式的直流失调校准电路,进一步提高了混频器的线性度;对跨阻放大器中的跨导运算放大器电路进行优化设计以提高其带宽,使跨阻放大器的输入阻抗足够小以保证混频器的线性度;基于180 nm RF CMOS工艺,对混频器进行仿真:当本振频率为2.4 GHz时,四档增益分别为38、32、27和21 dB,中频带宽可达20 MHz;噪声系数在高增益的情况下为8.46 dB,输入三阶交调点在低增益的情况下可达13.72 dBm;仿真结果表明,在较宽的中频带宽下,电流模式混频器取得了良好的线性度性能,满足WLAN接收机的定制化需求。

带有DCOC结构的中频可编程增益放大器

介绍了一种用于射频识别接收机、能有效消除直流失调的中频可编程增益放大器。单级放大器的仿真结果可提供-10～20dB的增益控制范围,增益步长为2dB,增益误差小于0.3dB。通过在直流失调消除环路中增加一级滤波器的方法,有效地降低了直流失调和低频噪声,在40kHz工作频率下等效输入噪声电压38.04nV/Hz,直流失调消除电路可将输出直流失调量抑制在输入失调量的2%范围以内。电路采用0.18μm1P6MCMOS工艺实现。

ADC参数对光栅莫尔信号细分影响研究

莫尔信号细分是光栅传感器应用的必要环节,幅值分割法是实现莫尔信号细分的重要手段。为减小信号质量对细分结果造成的影响,误差补偿成为细分实现过程中必不可少的单元。本文针对数字式幅值细分方法开展研究,针对ADC参数对光栅莫尔信号误差补偿和细分效果的影响进行分析,建立ADC参数与莫尔信号直流补偿、幅值补偿和细分倍数之间的量化模型,设计并开展了直流和幅值补偿效果实验。研究结果表明:不同位宽的ADC对莫尔信号误差补偿和细分效果的影响不同,在本文模型的基础上,ADC位宽应提高1 bit^2 bit。研究成果对于莫尔信号数字式幅值分割细分系统的工程实现具有一定的指导意义和参考价值。

一种新型双端口三电平变换器

针对传统背靠背三电平变换器成本高、体积大、结构复杂等问题,文中提出一种新型双端口三电平变换器拓扑,通过器件复用方式减少开关器件数量,优化系统结构。首先,详细分析所提新型拓扑的工作原理,给出单相桥臂的6种有效开关状态、电流流通路径及对应双端口输出电平,并对各开关器件的电压应力进行分析。其次,研究并设计一种适用于该新型拓扑的载波层叠脉宽调制策略,加入直流偏移量以避免调制波重合产生的影响。然后,进一步分析该策略在同频与异频工作模式下的调制度范围、相角差约束等关键问题,给出各工作模式下直流偏移量选取原则及两端口调制度约束范围。最后,基于DSP-FPGA-Typhoon HIL 402实验平台对不同工作模式进行验证。实验结果表明,在实现所提新型拓扑双端口电压电流稳定输出的前提下,加入直流偏移量的载波层叠脉宽调制策略使得变换器输出的电能质量良好,谐波含量低。

基于DC-DC升压和LC振荡的叠层压电陶瓷驱动电源研究

根据叠层压电陶瓷的大容性负载特性,在电路分析的基础上提出了基于DC-DC升压变换器和LC振荡的驱动控制电源,在驱动电路中加入偏置电压,使输出电压在-20V到100V之间,满足叠层压电陶瓷的驱动要求。将此驱动器用于压电直线电机,电机运转平稳,电路功耗小,通过匹配不同的电感实现了宽频率范围驱动。

零中频接收机DC偏移和IM2消除的探讨

由电路的不平衡和非线性引起的直流漂移 (DC offset)及混频器 RF信号泄漏引起的二阶互调干扰 (IM2 )是零中频接收机存在的一个主要问题 ,由于低频干扰信号 IM2的带宽与射频信号的幅度调制特性有关 ,因而很难通过固定的滤波器移除。通过对混频输出中的干扰信号进行估计 ,使用 DSP自适应非线性均衡的方法产生一个矫正信号 ,与混频器输出信号对消 ,以达到消除缓变 DC漂移和 IM2失真的目的。试验结果表明 。

基于云边协同的交直流混联电网线路过负荷协调控制方法

针对交直流混联电网线路过负荷影响因素较多导致线路运行特征难捕捉、难以实现精准控制的问题,提出基于云边协同的过负荷协调控制方法。建立过负荷状态数学模型,采用解耦算法求解不同程度过负荷情况下电力参数增量值并进行特征提取,将其作为云边协同算法的云计算参照值,获得同时符合功率最佳、能耗最小以及避免切负荷要求的协调控制参数,实现协调控制。实验结果表明:云边协同方法在盲区约束下可以准确检测盲区以外的所有节点,未出现漏检现象;光伏、风电出力的节点功率变化明显高于正常节点,节点过负荷控制效果较好。

Design of low-offset low-power CMOS amplifier for biosensor application

A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offset rejection scheme, the IC achieves lower offset voltage and lower power consumption compared to previous designs. This configuration rejects large DC offset and drift that exist at the skin-electrode interface without the need of external components. The proposed amplifier has been implemented in SMIC 0.18-μm 1P6M CMOS technol-ogy, with an active silicon area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV, the offset drift about 0.27 μV/℃ for temperature ranging from –30℃ to 100℃ and the total power dissipation consumed as low as 37.8 μW from a 1.8 V single supply. It dedicated to monitor low amplitude biomedical signals recording.

7.5位万用表精密放大器直流偏置问题研究

作为校准级仪器的7.5位万用表,可用于航天航空领域中传感器电参数标定。直流放大器的偏置问题直接影响万用表测量精度。本文设计一种低直流偏置放大器,以JFET构成的共源共基放大电路、比例缓冲电流镜、V-I变换恒流源电路作为输入级放大电路,级联高增益运算放大器构成电压串联负反馈结构,解决高输入阻抗与低噪声放大的矛盾问题。本文对失调电压和温度漂移构成的直流偏置模型进行分析:发现电流镜失调电压对JFET的失调电压具有补偿作用,并优化电阻修调电路对改善JFET失调电压;由温度漂移仿真发现:由V-I变换电流源的电流温度漂移和比例电阻温度漂移是放大器温度漂移的两大因素。通过低温漂敏感器件的选择、PCB热布局的优化及防风壳的设计,改善系统整体温度系数。实验表明,该放大器失调电压绝对值小于11μV,优于JFET类型精密放大器OPA828;放大器温度系数为-2~-4μV/℃,与没有温度校准的Keysight 3458A温度系数处于同一等级。该放大器满足7.5位万用表的设计需求。