A fourth-order low-distortion low-pass sigma-delta (∑△) modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to d...A fourth-order low-distortion low-pass sigma-delta (∑△) modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to decrease the nonlinearities and power consumption. The IC is implemented in a standard 0.6 μm CMOS technology and operates at a sampling frequency of 3.846 MHz. The chip area is 2.12 mm^2 with 23 pads. The experimental results indicate a signal-to-noise ratio (SNR) of 100 dB and dynamic range (DR) of 103 dB at an oversampling rate (OSR) of 128 with the input signal amplitude of-3.88 dBFS at 9.8 kHz; the power consumption is 15 raW at a 5 V supply.展开更多
In this paper a 0.6 V, 14 bit/500 Hz subthreshold inverter-based sigma-delta modulator is proposed. In the first integrator of the modulator, a bootstrap switch is used to accomplish accurate signal sampling. Without ...In this paper a 0.6 V, 14 bit/500 Hz subthreshold inverter-based sigma-delta modulator is proposed. In the first integrator of the modulator, a bootstrap switch is used to accomplish accurate signal sampling. Without a transconductor operational amplifier(OTA), the sigma-delta modulator adopts a cascode inverter in the subthreshold region to save power consumption. The modulator is fabricated with a 0.13μm CMOS mixed-signal process. The experiment results show that with the 0.6 V power supply it achieves a maximum SNDR of 69.7 dB and an ENOB of 11.3 bit, respectively, but only consumes 5.07 μw power dissipation.展开更多
Oversampling sigma–delta(Σ–Δ)analog-to-digital converters(ADCs)are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes h...Oversampling sigma–delta(Σ–Δ)analog-to-digital converters(ADCs)are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed.Structurally,theΣ–ΔADC is divided into two parts:a front-end analog modulator and a back-end digital filter.The performance of the front-end analog modulator has a marked influence on the entireΣ–ΔADC system.In this paper,a 4-order single-loop switched-capacitor modulator with a CIFB(cascade-of-integrators feed-back)structure is proposed.Based on the chosen modulator architecture,the ASIC circuit is implemented using a chartered 0.35μm CMOS process with a chip area of 1.72×0.75 mm^2.The chip operates with a 3.3-V power supply and a power dissipation of 22 mW.According to the results,the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits(ENOB)was almost 18-bit.展开更多
Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter applic...Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.展开更多
A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise rat...A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise ratio( SNR) of the EF-DSM is derived for different bus-splitting bits.Following the EF-DSM,a multi-bit digital up mixer is used for carrier frequency transform. In order to validate the theory of bus-splitting,two types of transmitters are implemented on FPGA for comparison,in which one is with non-bus-splitting and the other is with bus-splitting. The FPGA implemented transmitter with bus-splitting promotes the maximum operation speed by 39%,and reduces hardware consumptions more than 16%. Both single tone and orthogonal frequency division multiplexing( OFDM) signal source are used to evaluate the proposed transmitter.展开更多
A single die 1.2 V multi-stage noise shaping(Mash) 2-2 delta sigma analog to digital converter(ADC)for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is p...A single die 1.2 V multi-stage noise shaping(Mash) 2-2 delta sigma analog to digital converter(ADC)for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range(DR) for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb(CIC) filter and two half-band filters(HBF). The serial peripheral interface(SPI) can be used to adjust the sampling frequency and the oversampling ratio(OSR). The design was fabricated in a 0.13 m CMOS process with an area of 0.91 mm2and a total power of 5.2 mW. The measurement results show that the dynamic range(DR) of the proposed ADC can change from 55to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range(SFDR) and signal-to-noise distortion ratio(SNDR) can get 99 dB and 86.5 dB, respectively.展开更多
One of the major challenges in the field of motors is to improve rotation ripples. There are several causes of rotation ripples. This paper focuses on variations of manufacturing of a stator coil and proposes a new te...One of the major challenges in the field of motors is to improve rotation ripples. There are several causes of rotation ripples. This paper focuses on variations of manufacturing of a stator coil and proposes a new technique called DTMM (dynamic multi-coils-motor three-phase matching) based on the conventional NSDEM (noise shaping dynamic element matching). With DTMM, all the moving elements are shuffled while a single moving element is shuffled with NSDEM. Results show that the proposed system reduces the rotation ripple by 30% compared to the conventional PWM driving technology.展开更多
This paper introduces a mixed continuous-time/discrete-time, single-loop, fourth-order, 4-bit audioband sigma delta ADC that combines the benefits of continuous-time and discrete-time circuits, while mitigating the ch...This paper introduces a mixed continuous-time/discrete-time, single-loop, fourth-order, 4-bit audioband sigma delta ADC that combines the benefits of continuous-time and discrete-time circuits, while mitigating the challenges associated with continuous-time design. Measurement results show that the peak SNR of this ADC reaches 100 dB and the total power consumption is less than 30 mW.展开更多
A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed nonidealities analysis (excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch) is perform...A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed nonidealities analysis (excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch) is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. A third-order continuous time sigma delta modulator comprises a third-order RC operational- amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.展开更多
A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-...A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.展开更多
A new digital audio processing system based on Nonuniform Sampling Delta Mod-ulation (NSDM) technique is presented in this paper. The performance of NSDM system is analysed. Theoretical analysis and experimental resul...A new digital audio processing system based on Nonuniform Sampling Delta Mod-ulation (NSDM) technique is presented in this paper. The performance of NSDM system is analysed. Theoretical analysis and experimental results have demonstrated that the perfor-manc e of NSDM system used in digital audio is better than that of conventional Linear Delta Modulation (LDM) in terms of coding efficiency, Signal to Quantization-Noise Ratio and dy-namic range.展开更多
A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modula...A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.展开更多
基金supported by the National Natural Science Foundation of China(No.61204121)
文摘A fourth-order low-distortion low-pass sigma-delta (∑△) modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to decrease the nonlinearities and power consumption. The IC is implemented in a standard 0.6 μm CMOS technology and operates at a sampling frequency of 3.846 MHz. The chip area is 2.12 mm^2 with 23 pads. The experimental results indicate a signal-to-noise ratio (SNR) of 100 dB and dynamic range (DR) of 103 dB at an oversampling rate (OSR) of 128 with the input signal amplitude of-3.88 dBFS at 9.8 kHz; the power consumption is 15 raW at a 5 V supply.
基金Project supported by the National Natural Science Foundation of China(No.61704143)the Natural Science Foundation of Fujian Province(No.2018J01566)+1 种基金the Young and Middle-Aged Teacher Education Research Project of Fujian Province(No.JAT170428)the High-Level Talent Project of Xiamen University of Technology(No.YKJ17019R)
文摘In this paper a 0.6 V, 14 bit/500 Hz subthreshold inverter-based sigma-delta modulator is proposed. In the first integrator of the modulator, a bootstrap switch is used to accomplish accurate signal sampling. Without a transconductor operational amplifier(OTA), the sigma-delta modulator adopts a cascode inverter in the subthreshold region to save power consumption. The modulator is fabricated with a 0.13μm CMOS mixed-signal process. The experiment results show that with the 0.6 V power supply it achieves a maximum SNDR of 69.7 dB and an ENOB of 11.3 bit, respectively, but only consumes 5.07 μw power dissipation.
基金funded by the Major Emerging Industrial Projects of Anhuithe Postdoctoral Project from Hefei
文摘Oversampling sigma–delta(Σ–Δ)analog-to-digital converters(ADCs)are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed.Structurally,theΣ–ΔADC is divided into two parts:a front-end analog modulator and a back-end digital filter.The performance of the front-end analog modulator has a marked influence on the entireΣ–ΔADC system.In this paper,a 4-order single-loop switched-capacitor modulator with a CIFB(cascade-of-integrators feed-back)structure is proposed.Based on the chosen modulator architecture,the ASIC circuit is implemented using a chartered 0.35μm CMOS process with a chip area of 1.72×0.75 mm^2.The chip operates with a 3.3-V power supply and a power dissipation of 22 mW.According to the results,the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits(ENOB)was almost 18-bit.
基金Supported by the National Natural Science Foundation of China(No.61674037)the National Key Research and Development Program of China(No.2016YFC0800400)+2 种基金the Priority Academic Program Development of Jiangsu Higher Education Institutionsthe National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)the State Grid Nanjing Power Supply Company Project(No.1701052)
文摘Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.
基金Supported by the National Natural Science Foundation of China(No.61674037)National Key Research and Development Program of China(No.2016YFC0800400)+1 种基金the Priority Academic Program Development of Jiangsu Higher Education Institutionsthe National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)
文摘A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise ratio( SNR) of the EF-DSM is derived for different bus-splitting bits.Following the EF-DSM,a multi-bit digital up mixer is used for carrier frequency transform. In order to validate the theory of bus-splitting,two types of transmitters are implemented on FPGA for comparison,in which one is with non-bus-splitting and the other is with bus-splitting. The FPGA implemented transmitter with bus-splitting promotes the maximum operation speed by 39%,and reduces hardware consumptions more than 16%. Both single tone and orthogonal frequency division multiplexing( OFDM) signal source are used to evaluate the proposed transmitter.
基金Project supported by the National Natural Science Foundation of China(No.60976026)the Guangdong Industry University Research Cooperation Project(No.2011A090200106)+1 种基金the Guangdong Industry University High-Tech Development Guidance(No.2011B010700065)the Second Batch of Strategic Development Special Fund(No.2011912004)
文摘A single die 1.2 V multi-stage noise shaping(Mash) 2-2 delta sigma analog to digital converter(ADC)for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range(DR) for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb(CIC) filter and two half-band filters(HBF). The serial peripheral interface(SPI) can be used to adjust the sampling frequency and the oversampling ratio(OSR). The design was fabricated in a 0.13 m CMOS process with an area of 0.91 mm2and a total power of 5.2 mW. The measurement results show that the dynamic range(DR) of the proposed ADC can change from 55to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range(SFDR) and signal-to-noise distortion ratio(SNDR) can get 99 dB and 86.5 dB, respectively.
文摘One of the major challenges in the field of motors is to improve rotation ripples. There are several causes of rotation ripples. This paper focuses on variations of manufacturing of a stator coil and proposes a new technique called DTMM (dynamic multi-coils-motor three-phase matching) based on the conventional NSDEM (noise shaping dynamic element matching). With DTMM, all the moving elements are shuffled while a single moving element is shuffled with NSDEM. Results show that the proposed system reduces the rotation ripple by 30% compared to the conventional PWM driving technology.
文摘This paper introduces a mixed continuous-time/discrete-time, single-loop, fourth-order, 4-bit audioband sigma delta ADC that combines the benefits of continuous-time and discrete-time circuits, while mitigating the challenges associated with continuous-time design. Measurement results show that the peak SNR of this ADC reaches 100 dB and the total power consumption is less than 30 mW.
基金Project supported by the National Science and Technology Major Projects,China(No.2010ZX03006-003-02)
文摘A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed nonidealities analysis (excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch) is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. A third-order continuous time sigma delta modulator comprises a third-order RC operational- amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.
基金Project Supported by the Important National Science & Technology Specific Projects of China(No.2009ZXO1O31-003-002)the State Key Laboratory Project of China(No.11MS002)
文摘A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.
文摘A new digital audio processing system based on Nonuniform Sampling Delta Mod-ulation (NSDM) technique is presented in this paper. The performance of NSDM system is analysed. Theoretical analysis and experimental results have demonstrated that the perfor-manc e of NSDM system used in digital audio is better than that of conventional Linear Delta Modulation (LDM) in terms of coding efficiency, Signal to Quantization-Noise Ratio and dy-namic range.
基金supported by the National Natural Science Foundation of China(No.60236020)the Scientific Research Common Program of Beijing Municipal Commission of Education(No.KM201211232018)the Natural Science Foundation of Beijing City(No.4112029)
文摘A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.