The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network con...The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network consisting of a phase shifter is proposed. The phase shifter replaces the digital to analog converter （DAC） in the proposed architecture. Feasibility of the proposed idea is discussed and its higher performance is illustrated through a behavioral simulation approach （CppSim）. We have also developed the phase shifter as a variable all-pass filter in the C language. The nonlinearity and mismatch of the system caused by DAC is mitigated, resulting in higher signal to noise ratio （SNR） and signal to noise and distortion ratio （SNDR）, respectively.展开更多
This paper presents a proposed low-noise and high-sensitivity Internet of Thing(IoT)system based on an M&NEMS microphone.The IoT device consists of an M&NEMS resistive accelerometer associated with an electron...This paper presents a proposed low-noise and high-sensitivity Internet of Thing(IoT)system based on an M&NEMS microphone.The IoT device consists of an M&NEMS resistive accelerometer associated with an electronic readout circuit,which is a silicon nanowire and a Continuous-Time(CT)△∑ADC.The first integrator of the△∑ADC is based on a positive feedback DC-gain enhancement two-stage amplifier due to its high linearity and low-noise operations.To mitigate both the offset and 1/f noise,a suggested delay-time chopper negative-R stabilization technique is applied around the first integrator.A 65-nm CMOS process implements the CT△∑ADC.The supply voltage of the CMOS circuit is 1.2-V while 0.96-mW is the power consumption and 0.1-mm^(2) is the silicon area.The M&NEMS microphone and△∑ADC complete circuit are fabricated and measured.Over a working frequency bandwidth of 20-kHz,the measurement results of the proposed IoT system reach a signal to noise ratio(SNR)of 102.8-dB.Moreover,it has a measured dynamic range(DR)of 108-dB and a measured signal to noise and distortion ratio(SNDR)of 101.3-dB.展开更多
This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to...This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging （DCS-DWA） technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit（FOM） of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.展开更多
针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损...针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。展开更多
基金supported by Iran Telecommunication Research Center under Grant No. 4222/500
文摘The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network consisting of a phase shifter is proposed. The phase shifter replaces the digital to analog converter （DAC） in the proposed architecture. Feasibility of the proposed idea is discussed and its higher performance is illustrated through a behavioral simulation approach （CppSim）. We have also developed the phase shifter as a variable all-pass filter in the C language. The nonlinearity and mismatch of the system caused by DAC is mitigated, resulting in higher signal to noise ratio （SNR） and signal to noise and distortion ratio （SNDR）, respectively.
文摘This paper presents a proposed low-noise and high-sensitivity Internet of Thing(IoT)system based on an M&NEMS microphone.The IoT device consists of an M&NEMS resistive accelerometer associated with an electronic readout circuit,which is a silicon nanowire and a Continuous-Time(CT)△∑ADC.The first integrator of the△∑ADC is based on a positive feedback DC-gain enhancement two-stage amplifier due to its high linearity and low-noise operations.To mitigate both the offset and 1/f noise,a suggested delay-time chopper negative-R stabilization technique is applied around the first integrator.A 65-nm CMOS process implements the CT△∑ADC.The supply voltage of the CMOS circuit is 1.2-V while 0.96-mW is the power consumption and 0.1-mm^(2) is the silicon area.The M&NEMS microphone and△∑ADC complete circuit are fabricated and measured.Over a working frequency bandwidth of 20-kHz,the measurement results of the proposed IoT system reach a signal to noise ratio(SNR)of 102.8-dB.Moreover,it has a measured dynamic range(DR)of 108-dB and a measured signal to noise and distortion ratio(SNDR)of 101.3-dB.
基金supported by the National Natural Science Foundation of China(No.60906012)
文摘This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging （DCS-DWA） technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit（FOM） of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.
文摘针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。
