Ontology-supported and XML-based knowledge description language

Differences in the structure and semantics of knowledge that is created and maintained by the various actors on the World Wide Web make its exchange and utilization a problematic task. This is an important issue facing organizations undertaking knowledge management initiatives. An XML-based and ontology-supported knowledge description language (KDL) is presented, which has three-tier structure (core KDL, extended KDL and complex KDL), and takes advantages of strong point of ontology, XML, description logics, frame-based systems. And then, the framework and XML based syntax of KDL are introduced, and the methods of translating KDL into first order logic (FOL) are presented. At last, the implementation of KDL on the Web is described, and the reasoning ability of KDL proved by experiment is illustrated in detail.

The Logic Description of the System of Embedded Hardware Logic Task

A new task mode, hardware logic task mode, is presented. Its architecture, schedule and implementation are described with HDI.（ Hardware Description Language ）, and the validity of the system has been proved by logic simulation. It has advantage for real-time applications and overheadsaving for operating .system, so it is profitable for the controller in the embedded system. The relationship among RTOS （Real-Time Operating System）, SoC（System on Chip）, VIA （Virtual Interface Architecture） and hardware logic task is also discussed in the paper.

Typed formal model for WS-CDL specification of web services composition

In order to formally reason and verify web services composition described by web services choreography specification WS-CDL,a typed formal model named typed Abstract WS-CDL（web services choreography description language）for WS-CDL specifications is proposed.In typed Abstract WS-CDL,the syntax of type and session,typing rules and operational semantics are formalized;the collaborations of web services are formally described by sessions;the operational semantics of a session can help to formally reason the execution of the choreography;the typing rules can help to formally check the data type consistency of exchanged information between web services and capture run-time errors due to type mismatches.Particularly,the concepts of type assumption set extension and type assumption set compatibility are proposed,and the merging algorithm of type assumption sets is defined so as to eliminate type assumption conflict.Based on the formal model,typed mapping rules for mapping web services choreography to orchestration is also defined.With the typed mapping rules,orchestration stubs and their type assumption sets can be generated from a given choreography; thus, web services composition can be verified at choreography and orchestration levels,respectively.The model is proved to have properties of type safety,and how the model can help to reason and verify web services composition is illustrated through a case study.

ASIC Design of DA-Based 2-D Inverse Discrete Cosine Transform

Aim To present an ASIC design of DA based 2 D IDCT. Methods\ In the design of 1 D IDCT is utilized a Chen based fast IDCT algorithm, and multiplier accumulators based on distributed algorithm contributes in reducing the hardware amount and in enhancing the speed performance. Results and Conclusion\ VHDL simulation, synthesis and layout design of system are implemented. This 2 D IDCT ASIC design owns best timing performance when compared with other better designs internationally. Results of design prove to be excellent.

A Testing Method for Web Services Composition Based on Data-Flow

This paper proposes a method of data-flow testing for Web services composition. Firstly, to facilitate data flow analysis and constraints collecting, the existing model representation of business process execution language （BPEL） is modified in company with the analysis of data dependency and an exact representation of dead path elimination （DPE） is proposed, which over-comes the difficulties brought to dataflow analysis. Then defining and using information based on data flow rules is collected by parsing BPEL and Web services description language （WSDL） documents and the def-use annotated control flow graph is created. Based on this model, data-flow anomalies which indicate potential errors can be discovered by traversing the paths of graph, and all-du-paths used in dynamic data flow testing for Web services composition are automatically generated, then testers can design the test cases according to the collected constraints for each path selected.

An Intrusion Detection Algorithm for Wireless Networks Based on ASDL

Wireless networks are more vulnerable to cyberattacks than cable networks. Compared with the misuse intrusion detection techniques based on pattern matching, the techniques based on model checking(MC) have a series of comparative advantages. However, the temporal logics employed in the existing latter techniques cannot express conveniently the complex attacks with synchronization phenomenon. To address this problem, we formalize a novel temporal logic language called attack signature description language(ASDL). On the basis of it, we put forward an ASDL model checking algorithm. Furthermore, we use ASDL programs, which can be considered as temporal logic formulas,to describe attack signatures, and employ other ASDL programs to create an audit log. As a result, the ASDL model checking algorithm can be presented for automatically verifying whether or not the latter programs satisfy the formulas, that is, whether or not the audit log coincides with the attack signatures. Thus,an intrusion detection algorithm based on ASDL is obtained. The case studies and simulations show that the new method can find coordinated chop-chop attacks.

Design and Application of PCE-Oriented Multi-agent Software Framework and Agent Communication Module

With the improvement of mobile equipment performance and development of Pervasive Computing,interactive computational applications such as Multi-Agent (MA) systems in Pervasive Computing Environments (PCE) become more and more prevalent. Many applications in PCE require Agent communication,manual control,and diversity of devices. Hence system in PCE must be designed flexible,and optimize the use of network,storage and computing resources. However,traditional MA software framework cannot completely adapt to these new features. A new MA software framework and its Agent Communication Modules to solve the problem brought by PCE was proposed. To describe more precisely,it presents Wright/ADL (Architecture Description Language) description of the new framework. Then,it displays an application called AI Eleven based on this new framework. AI Eleven achieves Agent-Agent communication and good collaboration for a task. Two experiments on AI Eleven will demonstrate the new framework's practicability and superiority.

New Refinement Relations of Z Specifications for Multiple Viewpoints Oriented Requirements Method

In this paper we develop several new refinement relations of Z for multiple viewpoints oriented requirements method (MVORM). The original motivation is that we found the standard Z refinement relation is not adequate or correct when considering specifications that have temporal relationships of operations. The concept of temporal state variables is introduced into Z. Then new implementation relations are defined and new refinement relations are deduced, mainly for temporal state variables to process temporal relationships of operations. We use state transition systems to abstract the temporal state transitions. A simple example is used to show the procedures of MVORM. Finally some directions of further work are forwarded.

Generating test case specifications of web service composition using model checking

Model checking techniques have been widely used in verifying web service compositions to ensure the trustworthi- ness. However, little research has focused on testing web services. Based on the research of model checking techniques~ we propose a model checking based approach for testing web service composition which is described by using the web services choreography description language （WS-CDL）. According to worldwide web consortium （W3C） candidate recommendation, the WS-CDL specification provides a language for characterizing interactions between distinct web services using XML. Since the behaviors of web service composition are asynchronous, distributed, low-coupled and platform independent, we employ the guarded automata （GA） model for specifying the composition described in WS-CDL and using the simple promela interpreter （SPIN） model checker for detecting the collaborations of web services. Test cases can be transformed from counterexamples generated by SPIN using adequacy criteria. In this paper we apply the transition coverage criterion for generating counterex- amples. To illustrate our approach, we set ＂E-commerce service system＂ as an example for demonstrating how test cases can be generated using SPIN for compositions specified in WS-CDL.

A Q-based integrating interaction framework system for multi-agent coordination

Interaction is one of the crucial features of multl-agent systems, in which there are two kinds of interaction： agent-to-agent and human-to-agent. In order to unify the two kinds of interaction while designing multi-agent systems, this paper introduces Q language-a scenario description language for designing interaction among agents and humans. Based on Q, we propose an integrating interaction framework system for multi-agent coordination, in which Q scenarios are used to uniformly describe both kinds of interactions. Being in accordance to the characteristics of Q language, the Q-based framework makes the interaction process open and easily understood by the users. Additionally, it makes specific applications of multi-agent systems easy to be established by application designers. By applying agent negotiation in agent-mediated e-commerce and agent cooperation in interoperable information query on the Semantic Web, we illustrate how the presented framework for multi-agent coordination is implemented in concrete applications. At the same time, these two different applications also demonstrate usability of the presented framework and verify validity of Q language.

SF^2HDL： A Computational Tool of State Transition Diagram Translation

The lack of standard to electronic circuits modeling made possible the development of many tools and modeling languages for electronic circuits. In this way, several tools to be used on different descriptions stage of the designs are necessary. This paper presents a tool called SF^2HDL （Stateflow to Hardware Description Language or State Transition Table） that translates a finite state machine on state transition diagram representation, described by Stateflow tool, into an input file standard for TABELA program or into a file behavioral VHDL （Very High Speed Integrated Circuits Hardware Description Language） directly. The TABELA program was used to optimization this finite state machine. After that, the TAB2VHDL program was used to generate the VHDL code on register transfer level, what permits comparisons with results obtained by synthesis. The finite state machine must be described by Mealy model and the user can describe the machine on high level abstraction using all Simulink supports. The tool was very efficient on computational cost and it made translation of several cases, for the two VHDL description models. Every state machine translated was simulated and implemented on device EP2C20F484C7 using Quartus II environment.

Design and Verification of FPGA-Based Applications in Nuclear Power Plants

Nuclear industries have faced the unfavorable circumstance such as components obsolescence and aging of instrumentation and control system, therefore, nuclear society is striving to resolve this issue fundamentally. Various studies have been conducted to address components obsolescence of instrumentation and control system. Intuitively FPGA （field programmable gate arrays） technology is replacing the high level of micro-processor type equipped with various software and hardware which causes acceleration of the aging and obsolescence in I ＆ C （instrumentation and control） system in nuclear power plants. FPGAs are highlighted as an alternative means for obsolete control systems. When engineers design the control system of NPPs （nuclear power plants） with FPGAs, it is important to meet the system development life cycles and conduct the verification and validation activities regarding to FPGA-based applications for use in NPPs. Because the verification and validation process is more important than the design process, engineer should consider the characteristics of FPGA, HDL （hardware description language） programming, faults mode, and optimization technique. And also these characteristics should be reflected in verification and validation activities. As a minimum requirement, system designers require that HDL-programmed applications should be developed in accordance with system development life cycle and HPD design process. In the verification and validation processes, a review, test, and analysis activities should be properly conducted.

High-Performance FIR Filter Implementation Using Anurupye Vedic Multiplier

In this, today’s world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal. In any processor, the performance of the system is based on the speed of the multiplier unit involved in its operation. Since multiplier forms the indispensable building blocks of the FIR filter system. Its performance has contributed in determining the execution of the FIR filter system. Also, due to the tremendous development in the technology, many approaches such as an array, Vedic methods are made to speed up the multiplier computations. The problem in speed-up operation and resource utilization of hardware with all the conventional methods due to the critical path found in partial products has to be optimized using proposed method. This paper presents the implementation and execution of a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam, and array multipliers. The FIR filter is simulated for analyzing delay;area and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR filter design utilizing proposed multiplier offers delay around 18.99 and only 4% of LUT slice utilization compared to existing methods. This architecture is coded in VHDL, simulated using the ModelSim and synthesized with Xilinx.

xBreeze/ADL:A Language for Software Architecture Specification and Analysis

Architecture description languages play an important role in modelling software architectures. However, many architecture description languages （ADLs） are either unable to deal with the verification and dynamic changes directly or too formal to be understood and manipulated. This paper presents xBreeze/ADL, a novel extensible markup language （XML）-based verification and evolution supported architecture description language, which is specifically designed for modelling the software architecture of large, complex systems. Five principle design goals are 1） to separate template from instance to define a loose coupling structure, 2） to present virtual and concrete link to identify service execution flow, 3） to clearly represent component behaviour to specify architecture semantics, 4） to introduce multi-dimension restrictions to define the architecture constraints, and 5） to use the graph transformation theory to implement the architecture configuration management （i.e., reconfiguration and verification）. Various advanced features of xBreeze/ADL are illustrated by using an example on online movie ticket booking system.

Formal Description of the Crossing Social Network System Architecture Based on Temporal Logic

How to organize crossing social network resources on a higher level of integration and address them to users＇ desktops is an important difficult problem. Especially, there is a lack of efficient approaches to software architecture to build reusable system over the crossing social network, From the viewpoint of temporal logic XYZ/E, this paper proposes a kind of Architecture Descrip- tion Language about the Crossing Social Network system （CSN_ADL）, which can be used to depict the main key processes over the cross-social network system, and formally defines some key concepts, such as relation component, corelation component, override corelation connector, interaction connector, corelation network-oriented architecture, as well as system correctness, system activity, and system safety. Furthermore, some properties of correctness, activity, and safety under the flame CSN_ADL is discussed and depicted formally, which provides a formally theo- retical instruction for architecture reuses.

Design and implementation of high-speed real-time data acquisition system based on FPGA

The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.

Deadlock Detection in FPGA Design: A Practical Approach

Formal verification of VHSIC Hardware Description Language （VHDL） in Field-Programmable Gate Array （FPGA） design has been discussed for many years. In this paper we provide a practical approach to do so. We present a semi-automatic way to verify FPGA VHDL software deadlocks, especially those that reside in automata. A domain is defined to represent the VHDL modules that will be verified; these modules will be transformed into Verilog models and be verified by SMV tools. By analyzing the verification results of SMV, deadlocks can be found; after looking back to the VHDL code, the deadlocking code is located and the problem is solved. VHDL verification is particularly important in safety-critical software. As an example, our solution is applied to a Multifunction Vehicle Bus Controller （MVBC） system for a train. The safety properties were tested well in the development stage, but experienced a breakdown during the long-term software testing stage, which was mainly caused by deadlocks in the VHDL software. In this special case, we managed to locate the VHDL deadlocks and solve the problem by the FPGA deadlock detection approach provided in this paper, which demonstrates that our solution works well.

SPECIFYING AGENT-ORIENTED E-COMMERCE SOFTWARE AS ORGANIZATIONAL STRUCTURES

Agent architectures are gaining popularity for building open, distributed, and evolving software required by e-commerce applications. Unfortunately, despite considerable work in software architecture during the last decade, few research efforts have aimed at truly defining patterns and languages for agent architectural design. This paper proposes a modern approach based on organizational structures and architectural description languages to define and specify agent architectures notably in the case of e-commerce system design.

An Approach to Modelling and Analysing Reliability of Breeze/ADL-based Software Architecture

Breeze/architecture description language（ADL）, is an eX tensible markup language（XML） based architecture description language which is used to model software systems at the architecture level. Though Breeze/ADL provides an appropriate basis for architecture modelling, it can neither analyse nor evaluate the architecture reliability. In this paper, we propose a Breeze/ADL based strategy which, by combining generalized stochastic Petri net（GSPN） and tools for reliability analysis, supports architecture reliability modelling and evaluation. This work expands the idea in three directions： Firstly, we give a Breeze/ADL reliability model in which we add error attributes to Breeze/ADL error model for capturing architecture error information, and at the same time perform the system error state transition through the Breeze/ADL production. Secondly, we present how to map a Breeze/ADL reliability model to a GSPN model, which in turn can be used for reliability analysis. The other task is to develop a Breeze/ADL reliability analysis modelling tool–EXGSPN（Breeze/ADL reliability analysis modelling tool）, and combine it with platform independent petri net editor 2（PIPE2） to carry out a reliability assessment.Abstract： Breeze/architecture description language （ADL）, is an eXtensible markup language （XML） based architecture description language which is used to model software systems at the architecture level. Though Breeze/ADL provides an appropriate basis for architecture modelling, it can neither analyse nor evaluate the architecture reliability. In this paper, we propose a Breeze/ADL based strategy which, by combining generalized stochastic Petri net （GSPN） and tools for reliability analysis, supports architecture reliability modelling and evaluation. This work expands the idea in three directions： Firstly, we give a Breeze/ADL reliability model in which we add error attributes to Breeze/ADL error model for capturing architecture error information, and at the same time perform the system error state transition through the Breeze/ADL production. Secondly, we present how to map a Breeze/ADL reliability model to a GSPN model, which in turn can be used for reliability analysis. The other task is to develop a Breeze/ADL reliability analysis modelling tool-EXGSPN （Breeze/ADL reliability analysis modelling tool）, and combine it with platform independent petri net editor 2 （PIPE2） to carry out a reliability assessment.