Quantum algorithm for minimum dominating set problem with circuit design

Using quantum algorithms to solve various problems has attracted widespread attention with the development of quantum computing.Researchers are particularly interested in using the acceleration properties of quantum algorithms to solve NP-complete problems.This paper focuses on the well-known NP-complete problem of finding the minimum dominating set in undirected graphs.To expedite the search process,a quantum algorithm employing Grover’s search is proposed.However,a challenge arises from the unknown number of solutions for the minimum dominating set,rendering direct usage of original Grover’s search impossible.Thus,a swap test method is introduced to ascertain the number of iterations required.The oracle,diffusion operators,and swap test are designed with achievable quantum gates.The query complexity is O(1.414^(n))and the space complexity is O(n).To validate the proposed approach,qiskit software package is employed to simulate the quantum circuit,yielding the anticipated results.

SOME COMBINATORIAL OPTIMIZATION PROBLEMS ARISING FROM VLSI CIRCUIT DESIGN

This paper is basically a survey to show a number of combinatorial optimization problems arising from VLSI circuit design. Some of them including the existence problem, minimax problem, net representation, bend minimization, area minimization, placement problem, routing problem, etc. are especially discussed with new results and theoretical ideas for treating them. Finally, a number of problems for further research are mentioned.

A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

A new Rsslor hyperchaotic system and its realization with systematic circuit parameter design

Based on two modified Rosslor hyperchaotic systems, which are derived from the chaotic Rosslor system by introducing a state feedback controller, this paper proposes a new switched Rosslor hyperchaotic system. The switched system contains two different hyperchaotic systems and can change its behaviour continuously from one to another via a switching function. On the other hand, it presents a systematic method for designing the circuit of realizing the proposed hyperchaotic system. In this design, circuit state equations are written in normalized dimensionless form by rescaling the time variable. Furthermore, an analogous circuit is designed by using the proposed method and built for verifying the new hyperchaos and the design method. Experimental results show a good agreement between numerical simulations and experimental results.

Applications of modularized circuit designs in a new hyper-chaotic system circuit implementation

Modularized circuit designs for chaotic systems are introduced in this paper.Especially,a typical improved modularized design strategy is proposed and applied to a new hyper-chaotic system circuit implementation.In this paper,the detailed design procedures are described.Multisim simulations and physical experiments are conducted,and the simulation results are compared with Matlab simulation results for different system parameter pairs.These results are consistent with each other and they verify the existence of the hyper-chaotic attractor for this new hyper-chaotic system.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor (NMOS) and Complementary Metal Oxide Semiconductor (CMOS) latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company (TSMC) 0.25μm CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic (BCRL) and Pass-transistor Adiabatic Logic (PAL) including their clock generators is simulated. The simula-tion result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

DESIGN OF LIGHTWEIGHT PUF CIRCUIT BASED ON SELECTABLE CROSS-COUPLED INVERTERS

By analyzing the principle of process variations, a lightweight Physical Unclonable Function(PUF) circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation(SMIC) 65 nm CMOS technology and the layout area is 2.94 mm × 1.68 mm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.

Design of Digital Circuit Experiment Course Based on FPGA

With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.

LOW-FREQUENCY LOW-NOISE CIRCUITS DESIGN USING AN E_n-I_n MODEL

In view of the limitations of a Rn-Gn model in the low frequency range and the defects of an En-In model in common use now, this paper builds a complete En-In model according to the theory of random harmonic. The parameters for the low-noise design such as the equivalent input noisy voltage Ens, the optimum source impedance Zsopt and the minimum noise figure Fmin can be calculated accurately by using this En-In model because it considers the coherence between the noise sources fully. Moreover, this paper points out that it will cause the maximum 30% miscalculation when neglecting the effects of the correlation coefficient 7. Using the series-series circuits as an example, this paper discusses the methods for the En-In noise analysis of electronic circuits preliminarily and demonstrates its correctness through the comparison between the simulated and measured results of the minimum noise figure Fmin of a single current series negative feedback circuit.

Microwave Integrated Circuit Design Handbook

作者:Reinmut K.Hoffmann(1984 IEEE微波奖获得者) 出版:Artech House公司(美国)1987年本书给出适于微波工程师和研究人员应用的有关MIC方面的基础技术、电性能和设计。侧重于电性能分析和设计,强调应用。对于每一种设计技术和应用均作出较清楚的叙述和完整的处理。本书尽量给出电路的物理描述,避免过于冗长的数学公式,内容包含对下列议题的详细评述与研讨:

The Design of Circuit for Checking Short in HT-7U Superconducting Tokamak Device

The tokamak HT-7U project has been funded as a Chinese national project since 1998. The main object of the project is to build a nuclear fusion experimental device with divertor configuration, which is designed by the Institute of Plasma Physics, the Chinese Academy of Sciences (ASIPP). It is a full superconducting device, consisting of superconducting toroidal field (TF) coils and superconducting poloidal field (PF) coil. During the operation of the device, the operational parameter of device should be checked by technical diagnosis. This paper describes the design of circuit for checldng short between every two parts of the HT7U device. The main contents of design include circuit of data acquisition and data processing of computer.

A UNIFIED THEORY FOR DESIGNING ANDANALYZING BOTH SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.

Evolutionary Design of Fault-Tolerant Digital Circuit Based on Cartesian Genetic Programming

In many areas, reliability of the digital circuits has become the key factor to restrict circuit development. Fault-tolerant design is the commonly used method to improve the reliability of digital circuits. The current fault-tolerant design methods are based on triple modular redundancy( TMR) or multiple modular redundancy( MMR). These redundancy designs rely on the experience of the designers,and the designed circuits have poor adaptabilities to a complex environment. However, evolutionary design of digital circuits does not rely on prior knowledge. During the evolution, some novel and optimal circuit topologies can be found, and the evolved circuits can feature strong adaptive capacities. Based on Cartesian genetic programming( CGP), a novel method for designing fault-tolerant digital circuits by evolution is proposed,key steps of the evolution are introduced,influences of function sets on evolution are investigated,and as a preliminary result,an evolved full adder with high fault-tolerance is shown.

基于延边三角形接法的24脉波移相变压器设计与电磁特性分析

针对核心设备24脉波移相变压器,从移相原理出发进行设计,并建立场路耦合模型对电磁设计和绕组短路力进行核算,其中关键设计参数移相角与理论值最大偏差仅为0.53%。在此基础上加工实验样机进行实验,移相角度偏差最大仅为0.2°。综合仿真与实验结果,24脉波移相变压器设计有效,且场路耦合模型适用于多脉波移相变压器的电磁仿真。

Principle analysis and electromagnetic design of half－bridge commutating circuit for thyristor arc welding inverter

A novel theory of the commutating process of half/bridge thyristor are welding inverter is presented. According to the characteristic of its typical primary current pulse, a commutating process can be divided into three stages. ie.. front-edge wave-head stage and back-edge stage.The equivalent circuits of each stage are presented respectively. For wave-head stage, the differential equation about the voltage across commutating capacitor has been set up with the initial condition of nonzero-current and nonzero-voltage. and its solutions are completely in accord with the practically measured waveforms. For front and back edge stages, the theory of current shifting on constant magnetic condition is introduced. The process, in which the inverse voltage across commutating capacitor is formed, and the rule, according to which the inverse voltage varies.are discussed. In addition. each. special operating state is studied carefully and a reasonable design state is determined. By T-type equivalent circuit in the design. state. the fundamental formulas for accurate engineering design are derived. Finally. two design cases are given.

基于大动态范围放大的无增益调节超声放大电路设计

针对大型复合构件状态动态变化过程和多谱成像检测的需求,提出了一种无增益调节的宽带大动态范围超声放大电路的设计方法,设计了一种带宽为10 kHz~1.25 MHz,增益大于120 dB的无增益调节的超声信号放大电路。该电路采用多级放大器对信号进行分级放大,分割门限控制和信号状态识别与记录,最后通过数据合成实现了超声发射信号、回波信号全信号大动态、宽频带范围超声的放大。仿真实验表明,该电路可满足大型复合构件状态变化中信号的放大和多谱成像检测需求,其电路设计方法也可应用于其他如冲击波测试、声学测量等领域。

基于电流路径重构的无桥三电平PFC电路研究

文中提出一族电流路径重构的无桥三电平功率因数校正(power factor correction,PFC)电路,该族拓扑在无桥PFC的基础上,重构电流路径以减少电流路径中的功率器件,并保留无桥结构可靠性高和三电平结构器件应力低的优点。该族电路的任一工作模态仅需一个全控器件,有效降低全控器件损耗和电路控制复杂度。基于该族电路的工作原理分析,推导各器件应力、电压电流纹波与调制度的关系,利于元器件相关参数的设计,同时可推广到三电平电路拓扑的设计过程中;另外,设计该族电路调制技术及控制策略;最后,搭建实验样机,实验结果证明,该拓扑推衍方案的可行性和该族电路拓扑的有效性。