Generative Learning in VLSI Design for Manufacturability: Current Status and Future Directions

With the continuous scaling of integrated circuit technologies,design for manufacturability(DFM)is becoming more critical,yet more challenging.Alongside,recent advances in machine learning have provided a new computing paradigm with promising applications in VLSI manufacturability.In particular,generative learning-regarded among the most interesting ideas in present-day machine learning-has demonstrated impressive capabilities in a wide range of applications.This paper surveys recent results of using generative learning in VLSI manufacturing modeling and optimization.Specifically,we examine the unique features of generative learning that have been leveraged to improve DFM efficiency in an unprecedented way;hence,paving the way to a new data-driven DFM approach.The state-of-the-art methods are presented,and challenges/opportunities are discussed.

Design for manufacturability of a VDSM standard cell library

This paper presents a method of designing a 65 nm DFM standard cell library.By reducing the amount of the library largely,the process of optical proximity correction（OPC） becomes more efficient and the need for large storage is reduced.This library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical simulation.The area penalty is minor compared with traditional library,and the timing,as well as power has a good performance.Furthermore,this library has passed the test from the Technology Design Department of Foundry.The result shows this DFM standard cell library has advantages that improve the yield.

A Definition Formalism of Machining Features for DFM

Benefiting from advances in feature technology for design and manufacture can not be expected before a formal methodology is established. This paper makes attempt to establish a definition formalism of machining features in design for manufacturability from two aspects: formal definition and manufacturability analysis. Some definitions for machining feature based upon the selection and sequencing of material removal operations for component in accordance with the design geometry are presented and a framework of feature based design for manufacturability is outlined correspondingly. The proposed scheme contributes to several aspects of feature based CAD/CAM integration, especially to encourage potentially a more generic approach to the automation of design.

Full-IC manufacturability check based on dense silicon imaging

With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-RET sign-off verification is quickly becoming necessary. By introducing innovative algorithms for lithographic modeling, silicon imaging and yield problem locating, this paper describes a new methodology of IC manufacturability verification based on Dense Silicon Imaging (DSI). Necessity of imaging based verification is analyzed. Existing post-RET verification methods are reviewed and compared to the new methodology. Due to the greatly improved computational efficiency produced by algorithms such as the ~16*log2N/log2M times faster Specialized FFT, DSI based manufacturability checks on full IC scale, which were impractical for applications before, are now realized. Real verification example has been demonstrated and studied as well.

Structural topology optimization subject to overhang angle constraint with overhang length relaxation in additive manufacturing

This paper studies additive manufacturing(AM) oriented structural topology optimization(TO).The minimum compliance design subject to overhang angle constraint with overhang length relaxation and horizontal minimum length control is considered.Although the overhang length relaxation allows additional flexibility for AM product design,there have been very limited studies on it.This paper elucidates that the overhang angle constraint we proposed can identify the lower boundary element that violates the overhang angle constraint.Taking advantage of this fact,we achieve the overhang length relaxation by specifying that the volume fraction of the elements that violate the overhang angle constraint in each local area of the design domain is less than a specified upper bound.A formula for estimating the maximum allowable overhang length of this method is proposed and verified.The horizontal minimum length constraint is also employed in this paper.While controlling the horizontal length size of the structural member,this constraint together with the overhang angle constraint with overhang length relaxation suppresses the hanging feature.The gradient-based optimization algorithm method of moving asymptotic(MMA) is used to solve the TO formulation.Numerical examples show the effectiveness of this method.It is observed that the new constraint alleviates the main issues of traditional overhang angle constraints,i.e.,gray element issue,stress concentration issue,and shattered structure issue.Compared with the strict traditional overhang angle constraint,the new formulation reduces structural compliance.

Regular FPGA based on regular fabric

In the sub-wavelength regime,design for manufacturability（DFM） becomes increasingly important for field programmable gate arrays（FPGAs）.In this paper,an automated tile generation flow targeting micro-regular fabric is reported.Using a publicly accessible,well-documented academic FPGA as a case study,we found that compared to the tile generators previously reported,our generated micro-regular tile incurs less than 10%area overhead,which could be potentially recovered by process window optimization,thanks to its superior printability. In addition,we demonstrate that on 45 nm technology,the generated FPGA tile reduces lithography induced process variation by 33%,and reduce probability of failure by 21.2%.If a further overhead of 10%area can be recovered by enhanced resolution,we can achieve the variation reduction of 93.8%and reduce the probability of failure by 16.2%.