Low overhead design-for-testability for scan-based delay fault testing

An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.

Design for Testability Features of Godson-3 Multicore Microprocessor

This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

Study of testability measurement method for equipment based on Bayesian network model

To analyze and evaluate the testability design of equipment, a testability analysis method based on Bayesian network inference model is proposed in the paper. The model can adequately apply testability information and many uncertainty information of design and maintenance process, so it can analyze testability by and large from Bayesian inference. The detailed procedure to analyze and evaluate testability for equipments by Bayesian network is given in the paper. Its modeling process is simple, its formulation is visual, and the analysis results are more reliable than others. Examples prove that the analysis method based on Bayesian network inference can be applied to testability analysis and evaluation for complex equipments.

A DFT Method for Single-Control Testability of RTL Data Paths for BIST

This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.

Optimization method for diagnostic sequence based on improved particle swarm optimization algorithm

To realize the requirement of diagnostic sequence optimization in the process of design for testability, the authors put forward an optimization method based on quantum-behaved particle swarm optimization （QPSO） algorithm. By a precedence ordering coding, the diagnostic sequence optimization can be translated into a precedence ordering problem in the multidimensional space of swarm. It can get the optimizing order quickly by using the powerful and quick search capability of QPSO algorithm, and the order is the diagnostic sequence for the system. The realization of the method is simpler than other methods, and the results are more excellent than others, and it has been applied in the engineering practice.

Ethernet Controller SoC Design and Its Low-Power DFT Considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.

Area-time associated test cost model for SoC and lower bound of test time

A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.

GLOBAL: A Design for Random Testability Algorithm

A global design for testability algorithm is offered in this paper. First, a test point candidate set is obtained to simplify the test point placemellt problem; the principle of selective tracing is offered to get a sequential test point placement solution, which is used as the initial solution of the global algorithm. Using this initial value, a branch & bound algorithm is then offered to obtain a global design for testability solution. Finally,a new test length analyser is offered to evaluate the global design for testability.

A novel approach of testability modeling and analysis for PHM systems based on failure evolution mechanism

Prognostics and health management （PHM） significantly improves system availability and reliability, and reduces the cost of system operations. Design for testability （DFT） developed concurrently with system design is an important way to improve PHM capability. Testability modeling and analysis are the foundation of DFT. This paper proposes a novel approach of testability modeling and analysis based on failure evolution mechanisms. At the component level, the fault progression-related information of each unit under test （UUT） in a system is obtained by means of failure modes, evolution mechanisms, effects and criticality analysis （FMEMECA）, and then the failure-symptom dependency can be generated. At the system level, the dynamic attributes of UUTs are assigned by using the bond graph methodology, and then the symptom-test dependency can be obtained by means of the functional flow method. Based on the failure-symptom and symptom-test dependencies, testability analysis for PHM systems can be realized. A shunt motor is used to verify the application of the approach proposed in this paper. Experimental results show that this approach is able to be applied to testability modeling and analysis for PHM systems very well, and the analysis results can provide a guide for engineers to design for testability in order to improve PHM performance.

Test Vector Optimization Using Pocofan-Poframe Partitionin

This paper presents an automated POCOFAN-POFRAME algorithm thatpartitions large combinational digital VLSI circuits for pseudo exhaustive testing. In thispaper, a simulation framework and partitioning technique are presented to guide VLSIcircuits to work under with fewer test vectors in order to reduce testing time and todevelop VLSI circuit designs. This framework utilizes two methods of partitioningPrimary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning todetermine number of test vectors in the circuit. The key role of partitioning is to identifyreconvergent fanout branch pairs and the optimal value of primary input node N andfanout F partitioning using I-PIFAN algorithm. The number of reconvergent fanout andits locations are critical for testing of VLSI circuits and design for testability. Hence, theirselection is crucial in order to optimize system performance and reliability. In the presentwork, the design constraints of the partitioned circuit considered for optimizationincludes critical path delay and test time. POCOFAN-POFRAME algorithm uses theparameters with optimal values of circuits maximum primary input cone size (N) andminimum fan-out value (F) to determine the number of test vectors, number of partitionsand its locations. The ISCAS’85 benchmark circuits have been successfully partitioned,the test results of C499 shows 45% reduction in the test vectors and the experimentalresults are compared with other partitioning methods, our algorithm makes fewer testvectors.

Optimal Test Points Selection Based on Multi-Objective Genetic Algorithm

A new approach to select anoptimal set of test points is proposed. The described method uses fault-wise table and multi-objective genetic algorithm to find the optimal set of test points. First, the fault-wise table is constructed whose entries are measurements associated with faults and test points. The selection of optimal test points is transformed to the selection of the columns that isolate the rows of the table. Then, four objectives are described according to practical test requirements. The multi-objective genetic algorithm is explained. Finally, the presented approach is illustrated by a practical example. The results indicate that the proposed method can efficiently and accurately find the optimal set of test points and is practical for large scale systems.

A D-optimal Multi-position Calibration Method for Dynamically Tuned Gyroscopes

This paper presents a novel experimental design to greatly improve the calibration accuracy of the acceleration-insensitive bias and the acceleration-sensitive bias of the dynamically tuned gyroscopes（DTGs）.In order to reduce experimental cost,the D-optimal criteria with constraints are constructed.The turntable positions and the number of test points are chosen to build D-optimal experimental designs.The D-optimal experimental designs are tested by multi-position calibration experiment for tactical-grade DTGs.Test results show that,with the same cost,the fit uncertainty is reduced by about 50% by using the D-optimal 8-position experimental procedure,compared to using a defacto standard experimental procedure in ANSI/IEEE Std 813-1988.Furthermore,the new experimental procedure almost achieves optimal accuracy with only 12-position which is half the cost of the widely adopted 24-position experimental procedure for achieving optimal accuracy.

On GID-Testable Two-Dimensional Iterative Arrays

A new approach is presented for easily testable two-dimensional iterative arrays.It is an improvment on GI-testability (Group Identical testability) and is referred to as GID-testability (Group Identical and Different testability). In a GID-testable twodimensional array, the primary x and y outputs are organized into groups and every group has more than one output. This is similar to the GI-testable arrays. However,GID-testability not only ensures that identical test responses can be obtained from every output in the same group when an array is fault free, but also ensures that at least one output has different test responses (from the other outputs in a group) when a cell in the array is faulty Therefore, all faults can be detected under the assumption of a single faulty cell model. It is proved that an arbitrary two-dimensional iterative array is GID-testable if seven x-states and seven y-states are added to the original flow table of the basic cell of the array.GID-testability simplifies the response verification of built-in-self testing in a way similar to PL- and GI-testability[6-9]. Therefore, it is suitable for BIST design.