Differential Power Analysis (DPA) is an effective attack method to break the crypto chips and it has been considered to be a threat to security of information system. With analyzing the prin-ciple of resisting DPA,an ...Differential Power Analysis (DPA) is an effective attack method to break the crypto chips and it has been considered to be a threat to security of information system. With analyzing the prin-ciple of resisting DPA,an available countermeasure based on randomization is proposed in this paper. Time delay is inserted in the operation process and random number is precharged to the circuit during the delay time,the normal schedule is disturbed and the power is randomized. Following this meth-odology,a general DPA resistance random precharge architecture is proposed and DES algorithm following this architecture is implemented. This countermeasure is testified to be efficient to resist DPA.展开更多
This paper presents a method for designing a class of countermeasures for DPA attacks based on attenuation of current variations. In this class of countermeasures, designers aim at decreasing the dynamic current varia...This paper presents a method for designing a class of countermeasures for DPA attacks based on attenuation of current variations. In this class of countermeasures, designers aim at decreasing the dynamic current variations to reduce the information that can be extracted from the current consumption of secure microsystems. The proposed method is based on a novel formula that calculates the number of current traces required for a successful DPA attack using the characteristics of the microsystem current signal and the external noise of the measurement setup. The different stages of the proposed method are illustrated through designing an example current flattening circuit. Meanwhile validity and applicability of the proposed formula is verified by comparing theoretical results with those obtained experimentally for the example circuit. The proposed formula not only estimates the required level of attenuation for a target level of robustness defined by design requirements, it also predicts the effectiveness of a countermeasure using simulation results therefore dramatically reducing the time to design of secure microsystems.展开更多
This paper presents an effective way to enhance power analysis attacks on AES hardware implementations. The proposed attack adopts hamming difference of intermediate results as power mode. It arranges plaintext inputs...This paper presents an effective way to enhance power analysis attacks on AES hardware implementations. The proposed attack adopts hamming difference of intermediate results as power mode. It arranges plaintext inputs to differentiate power traces to the maximal probability. A simulation-based AES ASIC implementation and experimental platform are built. Various power attacks are conducted on our AES hardware implementation. Unlike on software implementations, conventional power attacks on hardware implementations may not succeed or require more computations. However, the method we proposed effectively improves the success rate using acceptable number of power traces and fewer computations. Furthermore from experimental data, the correlation factor between the hamming distance of key guesses and the difference of DPA traces has the value 0.9233 to validate power model and attack results.展开更多
DPA(Differential Power Analysis)攻击的强度取决于芯片电路功耗与所处理的数据之间的相关性以及攻击者对算法电路实现细节的了解程度.本文结合动态差分逻辑和可配置逻辑的特点,提出了一种具有抗DPA攻击能力的双端输出可配置逻辑(DRCL:...DPA(Differential Power Analysis)攻击的强度取决于芯片电路功耗与所处理的数据之间的相关性以及攻击者对算法电路实现细节的了解程度.本文结合动态差分逻辑和可配置逻辑的特点,提出了一种具有抗DPA攻击能力的双端输出可配置逻辑(DRCL:Dual-Rail Configurable Logic).该逻辑一方面具有与数据取值无关的信号翻转率和信号翻转时刻,因而能够实现很好的功耗恒定特性;另一方面去除了电路结构与电路功能之间的相关性,从而可以阻止攻击者通过版图逆向分析的方法窃取算法电路实现细节.实验结果表明,DRCL比典型的抗DPA攻击逻辑WDDL(Wave Dynamic Differential Logic)具有更好的功耗恒定性,因而具有更强的DPA攻击防护性能.展开更多
在密码算法电路中寄存器翻转时刻随机化对芯片抗DPA(differential power analysis)攻击能力有很大影响,因此提出了一种基于寄存器翻转时刻随机化的抗DPA攻击技术,其核心是利用不同频率时钟相位差的变化实现电路中关键寄存器翻转时刻的...在密码算法电路中寄存器翻转时刻随机化对芯片抗DPA(differential power analysis)攻击能力有很大影响,因此提出了一种基于寄存器翻转时刻随机化的抗DPA攻击技术,其核心是利用不同频率时钟相位差的变化实现电路中关键寄存器翻转时刻的随机变化.针对跨时钟域的数据和控制信号,提出了需要满足的时序约束条件的计算方法,同时还分析了不同时钟频率对寄存器翻转时刻随机化程度的影响.以AES密码算法协处理器为例,实现了所提出的寄存器翻转时刻随机化技术,通过实验模拟的方法验证了理论分析的正确性.实验结果显示,在合理选择电路工作时钟频率的情况下,所提出的技术能够有效提高密码算法电路的抗DPA攻击性能.展开更多
An embedded cryptosystem needs higher reconfiguration capability and security. After analyzing the newly emerging side-channel attacks on elliptic curve cryptosystem （ECC）, an efficient fractional width-w NAF （FWNA...An embedded cryptosystem needs higher reconfiguration capability and security. After analyzing the newly emerging side-channel attacks on elliptic curve cryptosystem （ECC）, an efficient fractional width-w NAF （FWNAF） algorithm is proposed to secure ECC scalar multiplication from these attacks. This algorithm adopts the fractional window method and probabilistic SPA scheme to reconfigure the pre-computed table, and it allows designers to make a dynamic configuration on pre-computed table. And then, it is enhanced to resist SPA, DPA, RPA and ZPA attacks by using the random masking method. Compared with the WBRIP and EBRIP methods, our proposals has the lowest total computation cost and reduce the shake phenomenon due to sharp fluctuation on computation performance.展开更多
文摘Differential Power Analysis (DPA) is an effective attack method to break the crypto chips and it has been considered to be a threat to security of information system. With analyzing the prin-ciple of resisting DPA,an available countermeasure based on randomization is proposed in this paper. Time delay is inserted in the operation process and random number is precharged to the circuit during the delay time,the normal schedule is disturbed and the power is randomized. Following this meth-odology,a general DPA resistance random precharge architecture is proposed and DES algorithm following this architecture is implemented. This countermeasure is testified to be efficient to resist DPA.
文摘This paper presents a method for designing a class of countermeasures for DPA attacks based on attenuation of current variations. In this class of countermeasures, designers aim at decreasing the dynamic current variations to reduce the information that can be extracted from the current consumption of secure microsystems. The proposed method is based on a novel formula that calculates the number of current traces required for a successful DPA attack using the characteristics of the microsystem current signal and the external noise of the measurement setup. The different stages of the proposed method are illustrated through designing an example current flattening circuit. Meanwhile validity and applicability of the proposed formula is verified by comparing theoretical results with those obtained experimentally for the example circuit. The proposed formula not only estimates the required level of attenuation for a target level of robustness defined by design requirements, it also predicts the effectiveness of a countermeasure using simulation results therefore dramatically reducing the time to design of secure microsystems.
文摘This paper presents an effective way to enhance power analysis attacks on AES hardware implementations. The proposed attack adopts hamming difference of intermediate results as power mode. It arranges plaintext inputs to differentiate power traces to the maximal probability. A simulation-based AES ASIC implementation and experimental platform are built. Various power attacks are conducted on our AES hardware implementation. Unlike on software implementations, conventional power attacks on hardware implementations may not succeed or require more computations. However, the method we proposed effectively improves the success rate using acceptable number of power traces and fewer computations. Furthermore from experimental data, the correlation factor between the hamming distance of key guesses and the difference of DPA traces has the value 0.9233 to validate power model and attack results.
文摘在密码算法电路中寄存器翻转时刻随机化对芯片抗DPA(differential power analysis)攻击能力有很大影响,因此提出了一种基于寄存器翻转时刻随机化的抗DPA攻击技术,其核心是利用不同频率时钟相位差的变化实现电路中关键寄存器翻转时刻的随机变化.针对跨时钟域的数据和控制信号,提出了需要满足的时序约束条件的计算方法,同时还分析了不同时钟频率对寄存器翻转时刻随机化程度的影响.以AES密码算法协处理器为例,实现了所提出的寄存器翻转时刻随机化技术,通过实验模拟的方法验证了理论分析的正确性.实验结果显示,在合理选择电路工作时钟频率的情况下,所提出的技术能够有效提高密码算法电路的抗DPA攻击性能.
基金supported by the National Natural Science Foundation of China(60373109)Ministry of Science and Technologyof China and the National Commercial Cryptography Application Technology Architecture and Application DemonstrationProject(2008BAA22B02).
文摘An embedded cryptosystem needs higher reconfiguration capability and security. After analyzing the newly emerging side-channel attacks on elliptic curve cryptosystem （ECC）, an efficient fractional width-w NAF （FWNAF） algorithm is proposed to secure ECC scalar multiplication from these attacks. This algorithm adopts the fractional window method and probabilistic SPA scheme to reconfigure the pre-computed table, and it allows designers to make a dynamic configuration on pre-computed table. And then, it is enhanced to resist SPA, DPA, RPA and ZPA attacks by using the random masking method. Compared with the WBRIP and EBRIP methods, our proposals has the lowest total computation cost and reduce the shake phenomenon due to sharp fluctuation on computation performance.
