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Design of power balance SRAM for DPA-resistance 被引量:1
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作者 周可基 汪鹏君 温亮 《Journal of Semiconductors》 EI CAS CSCD 2016年第4期106-112,共7页
A power balance static random-access memory(SRAM) for resistance to differential power analysis(DPA) is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanc... A power balance static random-access memory(SRAM) for resistance to differential power analysis(DPA) is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional shortcircuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm^2.The post-simulation results show that the normalized energy deviation(NED) and normalized standard deviation(NSD) are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%. 展开更多
关键词 differential power analysis(DPA) static random access memory(SRAM) power balance information security
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