The paper mainly focuses on the digital pulse width modulation (DPWM) control techniques for high performance power electronic circuit design. The problem to be solved in this study addresses the DPWM converter design...The paper mainly focuses on the digital pulse width modulation (DPWM) control techniques for high performance power electronic circuit design. The problem to be solved in this study addresses the DPWM converter design for DC to DC conversion process. The control techniques have been utilized the Fuzzy Logic Rules Base method for proposed SIMULINK model of high performance power electronic circuit. The analytical calculations for real circuit design have been completed based on the mathematical modeling of the system. The results from the developed SIMULINK model confirm the target specifications of the high performance condition for power electronic circuit which was met the objective of this study. The numerical results have been carried out with the help of MATLAB/SIMULINK.展开更多
为了降低CMOS降压型DC-DC变换器的功耗,提出了一种双延迟线结构数字脉宽调制器DPWM(Digital Pulse Width Modulator)设计。该DPWM架构由双延迟线组成,可以降低功耗并通过改变分辨率来提高纹波电压。通过使用8位和16位延迟线实现了虚拟12...为了降低CMOS降压型DC-DC变换器的功耗,提出了一种双延迟线结构数字脉宽调制器DPWM(Digital Pulse Width Modulator)设计。该DPWM架构由双延迟线组成,可以降低功耗并通过改变分辨率来提高纹波电压。通过使用8位和16位延迟线实现了虚拟128位延迟线,并提出了相应的DPWM控制算法。基于180 nm TSMC CMOS工艺,采用Cadence软件进行仿真分析。仿真和实际测量结果表明,提出的双延迟链DPWM功耗为1.18μW,纹波电压为10.4 m V。工作频率100 k Hz时在4 m A^10 m A的负载电流范围内,与传统转换器相比,具有所提出DPWM的DC-DC变换器实现了较高的峰值效率92.8%,且有效面积较小。展开更多
Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic...Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.展开更多
A small-signal model of current programmed mode pulse width modulation converter including the equivalent sampling effect is introduced and analyzed. In this model, an addition pole is brought out by the sampling effe...A small-signal model of current programmed mode pulse width modulation converter including the equivalent sampling effect is introduced and analyzed. In this model, an addition pole is brought out by the sampling effect in the current loop gain, and it affects dynamic bandwidth and stability of the inner current loop. By selecting the appropriate stability parameter which determines the additional pole and describes the degree of peaking in closed loop transfer function, a control model of current programmed full bridge arc welding inverter with maximum frequency bandwidth and stability can be obtained. Small and large amplitude pulse current outputs are employed in simulations and experiments and results validate the design method.展开更多
This paper models a low-power high-frequency digitally controlled synchronous rectifier （SR） OUCK converter. The converter is a hybrid system with three operation modes. Digital PID controler is used. Key problems s...This paper models a low-power high-frequency digitally controlled synchronous rectifier （SR） OUCK converter. The converter is a hybrid system with three operation modes. Digital PID controler is used. Key problems such as quantization resolution of digital pulse-width modulation （DPWM） and steady-state limit cycles of digital control switching model power supply （SMPS） are discussed, with corresponding solutions presented. Simulation of a digital control synchronous buck is performed with a fixed-point algorithm. The results show that the described approach enables high-speed dynamic performance.展开更多
文摘The paper mainly focuses on the digital pulse width modulation (DPWM) control techniques for high performance power electronic circuit design. The problem to be solved in this study addresses the DPWM converter design for DC to DC conversion process. The control techniques have been utilized the Fuzzy Logic Rules Base method for proposed SIMULINK model of high performance power electronic circuit. The analytical calculations for real circuit design have been completed based on the mathematical modeling of the system. The results from the developed SIMULINK model confirm the target specifications of the high performance condition for power electronic circuit which was met the objective of this study. The numerical results have been carried out with the help of MATLAB/SIMULINK.
文摘为了降低CMOS降压型DC-DC变换器的功耗,提出了一种双延迟线结构数字脉宽调制器DPWM(Digital Pulse Width Modulator)设计。该DPWM架构由双延迟线组成,可以降低功耗并通过改变分辨率来提高纹波电压。通过使用8位和16位延迟线实现了虚拟128位延迟线,并提出了相应的DPWM控制算法。基于180 nm TSMC CMOS工艺,采用Cadence软件进行仿真分析。仿真和实际测量结果表明,提出的双延迟链DPWM功耗为1.18μW,纹波电压为10.4 m V。工作频率100 k Hz时在4 m A^10 m A的负载电流范围内,与传统转换器相比,具有所提出DPWM的DC-DC变换器实现了较高的峰值效率92.8%,且有效面积较小。
基金supported by the National Natural Science Foundation of China(61401204)the Fundamental Research Funds for the Central Universities(30916011319)+1 种基金the Technology Research and Development Program of Jiangsu Province(BY2015004-03)the Postdoctoral Science Foundation of Jiangsu Province(1501104C)
文摘Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.
文摘A small-signal model of current programmed mode pulse width modulation converter including the equivalent sampling effect is introduced and analyzed. In this model, an addition pole is brought out by the sampling effect in the current loop gain, and it affects dynamic bandwidth and stability of the inner current loop. By selecting the appropriate stability parameter which determines the additional pole and describes the degree of peaking in closed loop transfer function, a control model of current programmed full bridge arc welding inverter with maximum frequency bandwidth and stability can be obtained. Small and large amplitude pulse current outputs are employed in simulations and experiments and results validate the design method.
基金the Power Electronics Science Education Development Program of Delta Environmental & EducationFoundation (Grant No.DERO2007014)the Scientific Service of the Embassy of France in China (Grant No.K06D20)
文摘This paper models a low-power high-frequency digitally controlled synchronous rectifier （SR） OUCK converter. The converter is a hybrid system with three operation modes. Digital PID controler is used. Key problems such as quantization resolution of digital pulse-width modulation （DPWM） and steady-state limit cycles of digital control switching model power supply （SMPS） are discussed, with corresponding solutions presented. Simulation of a digital control synchronous buck is performed with a fixed-point algorithm. The results show that the described approach enables high-speed dynamic performance.
