An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integra...An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift （SSFS） module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/（km.nm） with ＋0.5 ps/（km.nm） variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate （MSSR） is 50.45 GSa/s with full width at half maximum （FWHM） variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.展开更多
A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that ...A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.展开更多
A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC ...A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.展开更多
A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods...A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods should be studied to achieve optimum performance. Different sampling modes were used and compared through tests. Long term variation among four sampling channels, which would introduce errors in beam position measurement, is investigated. An interleaved distribution scheme was designed to address this issue. To evaluate the sampling methods, in-beam tests were conducted in SSRF. Test results indicate that with proper sampling methods, a turn-by-turn(TBT) position resolution better than 1 μm is achieved, and the slow-acquisition(SA) position resolution is improved from 4.28 μm to 0.17 μm.展开更多
数字接收系统中,对输入的射频信号直接中频采样后进行数字下变频(Digital Down Converter,DDC),有效减少了硬件模拟设备的数量,提高了系统的可靠性和稳定性。针对高速数字下变频存在的采样率高、资源消耗高等难点,利用滤波器系数的对称...数字接收系统中,对输入的射频信号直接中频采样后进行数字下变频(Digital Down Converter,DDC),有效减少了硬件模拟设备的数量,提高了系统的可靠性和稳定性。针对高速数字下变频存在的采样率高、资源消耗高等难点,利用滤波器系数的对称性特点设计了一种在不降低处理速度的前提下,减少现场可编程门阵列(Field ProgrammableGate Array,FPGA)内部处理单元个数,实现功耗降低的有限冲击响应(Finite Impulse Response,FIR)滤波器,并在FPGA中得到了实现。实验结果表明,该方法性能优异,可大幅节省资源,具有较高的工程实用价值。展开更多
This paper presents a flexible and high speed digital scan converter (DSC) with the ability to handle high frequency ultrasound imaging in real-time. The characteristics in imaging system such as focus length of trans...This paper presents a flexible and high speed digital scan converter (DSC) with the ability to handle high frequency ultrasound imaging in real-time. The characteristics in imaging system such as focus length of transducer, the swing radius and sampling length etc. could be changed easily in compliance with the researcher's application based on this flexible digital scan converter. Linear interpolation is employed to achieve the coordinate transformations algorithm. Custom-built software is programmed to preliminarily handle the algorithm according to different ultrasound imaging applications. High performance FPGA will implement high speed interpolation calculation based on the preliminary data which are stored in the DDR2 SDRAM from the software. 64 bit 66 MHz PCI is employed to accomplish high speed data transmission. Experiment has shown that more than 500 frame rate could be achieved based on this high speed digital scan converter. The designed flexible and high speed digital scan converter could be used in current FPGA based high frequency ultrasound imaging system.展开更多
基金supported by the Fundamental Research Funds for the Central Universities,China(Grant No.FRF-TP-15-030A1)China Postdoctoral Science Foundation(Grant No.2015M580978)
文摘An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift （SSFS） module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/（km.nm） with ＋0.5 ps/（km.nm） variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate （MSSR） is 50.45 GSa/s with full width at half maximum （FWHM） variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.
基金Supported by the National Defense Pre-research Fund of China
文摘A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.
文摘A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.
基金Supported by the Knowledge Innovation Program of the Chinese Academy of Sciences(No.KJCX2-YW-N27)National Natural Science Foundation of China(Nos.11205153 and 11175176)
文摘A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods should be studied to achieve optimum performance. Different sampling modes were used and compared through tests. Long term variation among four sampling channels, which would introduce errors in beam position measurement, is investigated. An interleaved distribution scheme was designed to address this issue. To evaluate the sampling methods, in-beam tests were conducted in SSRF. Test results indicate that with proper sampling methods, a turn-by-turn(TBT) position resolution better than 1 μm is achieved, and the slow-acquisition(SA) position resolution is improved from 4.28 μm to 0.17 μm.
文摘This paper presents a flexible and high speed digital scan converter (DSC) with the ability to handle high frequency ultrasound imaging in real-time. The characteristics in imaging system such as focus length of transducer, the swing radius and sampling length etc. could be changed easily in compliance with the researcher's application based on this flexible digital scan converter. Linear interpolation is employed to achieve the coordinate transformations algorithm. Custom-built software is programmed to preliminarily handle the algorithm according to different ultrasound imaging applications. High performance FPGA will implement high speed interpolation calculation based on the preliminary data which are stored in the DDR2 SDRAM from the software. 64 bit 66 MHz PCI is employed to accomplish high speed data transmission. Experiment has shown that more than 500 frame rate could be achieved based on this high speed digital scan converter. The designed flexible and high speed digital scan converter could be used in current FPGA based high frequency ultrasound imaging system.
