A digital time correlative accumulation(Ⅱ)——cross-correlative accumulation

The digital time cross-correlative accumulation ( DTCCA ) scheme is described in the paper. The basic principle and structure of the scheme are discussed first , the detection probability, false-alarm probability and input S/ N are then analyzed for some typical sonar systems . The superior performances have been proved true through theoretical estimations and field experiments . Like DTACA , the DTCCA , as a signal processing scheme , has a wide application in complicated shallow acoustical channel at low data rate.

A new method of aperture synthetizing in digital holography

This paper proposes a new method of aperture synthetizing in digital holography based on the principle of holography.In the new method aperture synthetizing is achieved by reconstructing each sub-hologram respectively,firstly,moving each reconstructed wave field referred to the benchmark reconstructed wave field according to the relationship between spacial motion and frequency shift,and finally splicing them by using superposition. Two different recording ways,using plane wave to record and using spherical wave to record,are analyzed,and their moving formula is deduced,too.Simulation and experiment are done. The results show that in comparison with the traditional method of aperture synthetizing in digital holography,the new method can decrease calculation and save reconstructed time obviously which has better applicability.

电压波动与闪变实时检测的数字化实现及仿真

基于平波调解检波法和IEC推荐的闪变检测原理建立了电压波动与闪变实时检测的数字化实现模型,并利用MATLAB进行了仿真。结果显示,数字化实验模型有一定误差,建议在设计数字滤波器时加入窗函数以提高滤波效果。

A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented.The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited.The proposed converter features high accuracy,very small average error and high linear range.Also this converter has some advantages such as low circuit complexity,low power consumption and low sensitive to the temperature,power supply and process changes(PVT)compared with the time to digital converters that used preceding conversion techniques.The proposed converter uses an indirect time to digital conversion method.Therefore,our converter has the appropriate linearity without extra elements.In order to evaluate the proposed idea,an integrating time to digital converter is designed in 0.18 lm CMOS technology and was simulated by Hspice.Comparison of the theoretical and simulation results confirms the proposed TDC operation;therefore,the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.

A programmable gain amplifier with digitally assisted DC offset calibration for a direct-conversion WLAN receiver

This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.

A high SFDR 6-bit 20-MS/s SAR ADC based on time-domain comparator

This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, especially for wireless sensor network（WSN） applications.This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology,the ADC performs a peak SFDR of 55.32 dB and effective number of bits（ENOB） of 5.1 bit for 10 MS/s.At the sample rate of 20 MS/s and the Nyquist input frequency,the 47.39-dB SFDR and 4.6-ENOB are achieved.The differential nonlinearity（DNL） is less than 0.83 LSB and the integral nonlinearity（INL） is less than 0.82 LSB.The experimental results indicate that this SAR ADC consumes a total of 522μW power and occupies 0.98 mm^2.

A novel hybrid cybersecurity scheme against false data injection attacks in automated power systems

The conventional power systems are evolving as smart grids.In recent times cyberattacks on smart grids have been increasing.Among different attacks,False Data Injection(FDI)is considered as an emerging threat that has significant impact.By exploiting the vulnerabilities of IEC 61850 Generic Object-Oriented Substation Events(GOOSE)and Sam-pled Values(SV)attackers can launch different FDI attacks.In this paper,a real-time set up capable of simulating FDI on GOOSE and SV protocols is developed to evaluate the impact of such attacks on power grid.IEC 62351 stipulates cybersecurity guidelines for GOOSE and SV,but only at communication or Information Technology(IT)level.Hence there is a need to develop a holistic security both at IT and Operation Technology(OT)level.In this regard,a novel sequence content resolver-based hybrid security scheme suitable to tackle FDI attacks on GOOSE and SV is proposed.Furthermore,the computational performance of the proposed hybrid security scheme is presented to demonstrate its applicability to the time critical GOOSE and SV protocols.

Modeling methodology and fault simulation of distribution networks integrated with inverter-based DG

The increasing penetration of inverter-based distributed generations(DGs)significantly affects the fault characteristics of distribution networks.Fault analysis is a keystone for suitable protection scheme design.This paper presents the modelling methodology for distribution networks with inverter-based DGs and performs fault simulation based on the model.Firstly,a single inverter-based DG model based on the cascaded control structure is developed.Secondly,a simulation model of distribution network with two inverter-based DGs is established.Then,different fault simulations are performed based on the Real Time Digital Simulator(RTDS).Theoretical analyses are conducted to justify the simulation results,including the equivalent circuit of distribution networks with inverter-based DGs and the solution method for loop currents.