With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co...With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.展开更多
This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. A...This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.展开更多
The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are inv...The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.展开更多
There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil t...There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.展开更多
A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sa...A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.展开更多
A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital c...A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.展开更多
为标定光交叉芯片驱动电压,控制光交叉芯片实现光路由功能,提出并搭建了基于多通道DAC(Digital to Analog Converter)阵列的控制驱动电路系统。系统主要由控制系统模块、多路驱动电路模块及上位机控制模块构成。控制电路和驱动电路具有...为标定光交叉芯片驱动电压,控制光交叉芯片实现光路由功能,提出并搭建了基于多通道DAC(Digital to Analog Converter)阵列的控制驱动电路系统。系统主要由控制系统模块、多路驱动电路模块及上位机控制模块构成。控制电路和驱动电路具有调校简单、可双极性输出、输出路数多、加电精确度较高的特点,解决了当前驱动电路工作繁琐、加电极性单一、加电路数少、精度差的问题。上位机控制模块除了可控制驱动电路施加控制电压外,还可接收来自数据采集装置采集到的光功率信号作为控制驱动系统的反馈信号。通过分析控制电压与光功率之间的关系,可得到最佳的光交叉芯片控制驱动电压。系统测试实验结果表明,该系统能提供高精确度的双极性驱动电压,有效地对光交叉芯片进行驱动。可在较短的时间内标定出光开关的控制电压,完全可以满足有源光交叉芯片控制中对驱动电压的需求。该系统在光交叉芯片控制方面具有一定的应用价值。展开更多
We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of pho...We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.展开更多
In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias...In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.展开更多
Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the ...Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.展开更多
A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital convert...A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.展开更多
A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, w...A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.展开更多
As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although convent...As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.展开更多
电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,...电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。展开更多
A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3...A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.展开更多
A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CO) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the prec...A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CO) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range (SFDR) of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio (SNDR) of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.展开更多
A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multiit multiply digital to analog converter sta...A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multiit multiply digital to analog converter stages are implemented. An on-chip low-noise reference buffer is proposed for SoC integration purposes, and a wide-bandwidth wide swing sample and hold amplifier is also presented for achieving a good dynamic range. The converter was fabricated in 0.18 #m 1P6M CMOS technology, and the core area occupies approximately 0.85 mm2. Measured results show that with an 11 MHz input signal, it provides a 9.4 bit effective number of bits and a 72 dBc spurious frequency dynamic range when sampled at 80 MHz.展开更多
文摘With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.
基金supported in part by the National Natural Science Foundation of China under Grant No.61006027the New Century Excellent Talents Program of the Ministry of Education of China under Grant No.NCET-10-0297the Fundamental Research Funds for Central Universities under Grant No.ZYGX2012J003
文摘This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.
基金supported by the National Natural Science Foundation of China (Grant No. 11205038)the China Postdoctoral Science Foundation (Grant No. 2012M510951)
文摘The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.
文摘There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.
基金The National Science Fund for Creative Re-search Groups( Grant No 60521002 )Shanghai Natural Science Foundation (GrantNo 037062022)
文摘A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.
文摘A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.
文摘为标定光交叉芯片驱动电压,控制光交叉芯片实现光路由功能,提出并搭建了基于多通道DAC(Digital to Analog Converter)阵列的控制驱动电路系统。系统主要由控制系统模块、多路驱动电路模块及上位机控制模块构成。控制电路和驱动电路具有调校简单、可双极性输出、输出路数多、加电精确度较高的特点,解决了当前驱动电路工作繁琐、加电极性单一、加电路数少、精度差的问题。上位机控制模块除了可控制驱动电路施加控制电压外,还可接收来自数据采集装置采集到的光功率信号作为控制驱动系统的反馈信号。通过分析控制电压与光功率之间的关系,可得到最佳的光交叉芯片控制驱动电压。系统测试实验结果表明,该系统能提供高精确度的双极性驱动电压,有效地对光交叉芯片进行驱动。可在较短的时间内标定出光开关的控制电压,完全可以满足有源光交叉芯片控制中对驱动电压的需求。该系统在光交叉芯片控制方面具有一定的应用价值。
文摘We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.
文摘In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.
文摘Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.
文摘A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.
基金Supported by the Doctoral Program Foundation of Institutions of Higher Education of China (No.20120111120008)State Key Lab of ASIC & System(Fudan University) (No. 11KF001)Special Fund for Doctoral Program (Hefei University of Technology) (No.2011HGBZ0953)
文摘A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.
基金This work was supported by the National Research Foundation of Korea(NRF)grant funded by theKorea government(MSIT)(No.2022R1A5A8026986)and supported by Institute of Information&communications Technology Planning&Evaluation(IITP)grant funded by the Korea government(MSIT)(No.2020-0-01304,Development of Self-learnable Mobile Recursive Neural Network Processor Technology)+3 种基金It was also supported by the MSIT(Ministry of Science and ICT),Korea,under the Grand Information Technology Research Center support program(IITP-2022-2020-0-01462)supervised by the“IITP(Institute for Information&communications Technology Planning&Evaluation)”supported by the National Research Foundation of Korea(NRF)grant funded by the Korea government(MSIT)(No.2021R1F1A1061314)In addition,this work was conducted during the research year of Chungbuk National University in 2020.
文摘As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.
文摘电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。
基金Project supported by the National Natural Science Foundation of China(Nos.60906009,60773025)the Postdoctoral Science Foundation of China(No.20090451423)the National Labs of Analog Integrated Circuits Foundation(No.9140C0901110902)
文摘A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.
基金supported by National Natural Science Foundation of China under grant No.61704161Key Project of Natural Science of Anhui Provincial Department of Education under grant No.KJ2017A396
文摘A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CO) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range (SFDR) of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio (SNDR) of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.
基金Project supported by the National Science & Technology Major Projects of China(No.2009ZX03007-002-03)
文摘A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multiit multiply digital to analog converter stages are implemented. An on-chip low-noise reference buffer is proposed for SoC integration purposes, and a wide-bandwidth wide swing sample and hold amplifier is also presented for achieving a good dynamic range. The converter was fabricated in 0.18 #m 1P6M CMOS technology, and the core area occupies approximately 0.85 mm2. Measured results show that with an 11 MHz input signal, it provides a 9.4 bit effective number of bits and a 72 dBc spurious frequency dynamic range when sampled at 80 MHz.