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Robustness Proof on A United Watermarking Based on CRT Theorem
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作者 LIULi-gang CHENXiao-su XIAODao-ju HULei 《Wuhan University Journal of Natural Sciences》 EI CAS 2005年第1期307-310,共4页
A new method of embedding and detecting a joint watermarking is proposed. Itapplies the asmuth-bloom secret sharing scheme, which is based on CRT (Chinese remainder theorem)theorem, to the digital watermarking technol... A new method of embedding and detecting a joint watermarking is proposed. Itapplies the asmuth-bloom secret sharing scheme, which is based on CRT (Chinese remainder theorem)theorem, to the digital watermarking technology. On the base of describing the watermarkingembedding proceeding and analyzing the watermarking detection proceeding, a series of experiments isdone. The experiments emphasize on the method's robust proving and security analysis. And theexperiments show that the method can resistthe attacks of JPEG compress, geometry, noise and grayadjusting. The results of the experiments show that the method has a nice recognition of copyrightfor joint ownership. 展开更多
关键词 united digital watermarking Chinese remainder theorem robustness proof
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A low power mixed signal DC offset calibration circuit for direct conversion receiver applications
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作者 杨利君 袁芳 +2 位作者 龚正 石寅 陈治明 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第12期134-138,共5页
A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die a... A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 ×0.419 mm^2. 展开更多
关键词 mixed signal DC offset calibration analog to digital converter digital control logic unit digital toanalog converter least significant bit
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