Measurement of soil electrical conductivity based on direct digital synthesizer(DDS)and digital oscilloscope

A soil electrical conductivity(EC)measurement system based on direct digital synthesizer(DDS)and digital oscilloscope was developed.The system took the“current-voltage four-electrode method”as the design principal and adopted a six-pin structure of the probe,two center pins to measure the soil EC in shallow layer,two outside pins to measure the soil EC in deep layer,and two middle pins for inputting the driving current.A signal generating circuit using DDS technology was adopted to generate sine signals,which was connected with the two middle pins.A digital oscilloscope was used to record and store the two soil output signals with noises in microseconds,which were from the two center pins and two outside pins,respectively.Then a digital bandpass filter was used to filter the soil output signals recorded by the digital oscilloscope.Compared with the traditional analog filter circuit,the digital filter could filter out the noises of all frequency except for the frequency of the excitation source.It could improve the effect of filtering and the accuracy of the soil EC measurement system.The DDS circuit could provide more stable sine signals with larger amplitudes.The use of digital oscilloscope enables us to analyze the soil output signals in microseconds and measure the soil EC more accurately.The new soil EC measurement system based on DDS and digital oscilloscope can provide a new effective tool for soil sensing in precision agriculture.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.

A high speed direct digital frequency synthesizer based on multi-channel structure

This paper presents a direct digital frequency synthesizer （DDFS） for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 x 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.

Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.

DDFS spurious signals due to amplitude quantization in absence of phase-accumulator truncation

Spurious signals in direct digital frequency synthesizers （DDFSs） are partly caused by amplitude quantization and phase truncation, which affect their application to many wireless telecommunication systems. These signals are deterministic and periodic in the time domain, so they appear as line spectra in the frequency domain. Two types of spurious signals due to amplitude quantization are exactly formulated and compared in the time and frequency domains respectively. Then the frequency spectra and power levels of the spurious signals due to amplitude quantization in the absence of phase-accumulator truncation are emphatically analyzed, and the effects of the DDFS parameter variations on the spurious signals are thoroughly studied by computer simulation. And several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.