Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel...Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage comparator.NMOS is used to reduce stacking leakage as well as total exchange.Domino Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent years.In this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino circuit.The efficiency and effec-tiveness of the domino circuit are demonstrated through simulation results.The suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of power.The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR gates.As per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits.展开更多
Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed. Eight-input OR gate circuits constructed with these techniques are simulated using 45n...Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed. Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE. The simulation results show that the proposed circuits effectively lower the active power, reduce the total leakage current, and enhance speed under similar noise immunity conditions. The active power of the two proposed circuits can be reduced by up to 8. 8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage. At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4% ,respectively. Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.展开更多
An improved high fan-in domino circuit is proposed. The nMOS pull-down network of the circuit is divided into several blocks to reduce the capacitance of the dynamic node and each block only needs a small keeper trans...An improved high fan-in domino circuit is proposed. The nMOS pull-down network of the circuit is divided into several blocks to reduce the capacitance of the dynamic node and each block only needs a small keeper transistor to maintain the noise margin. Because we omit the footer transistor, the circuit has better performance than the standard domino circuit. A 64-input OR-gate implemented with the structure is simulated using HSPICE under typical conditions of 0.13μm CMOS technology. The average delay of the circuit is 63.9ps, the average power dissipation is 32.4μW, and the area is l15μm^2. Compared to compound domino logic, the proposed circuit can reduce delay and power dissipation by 55% and 38%, respectively.展开更多
A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keep...A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper.Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also,a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.展开更多
We report a case of double domino liver transplantation in a 32-year-old woman who was diagnosed with familial amyloid polyneuropathy(FAP) and liver dysfunction. A two-stage surgical plan was designed, and one domino ...We report a case of double domino liver transplantation in a 32-year-old woman who was diagnosed with familial amyloid polyneuropathy(FAP) and liver dysfunction. A two-stage surgical plan was designed, and one domino graft was implanted during each stage. During the firststage, an auxiliary domino liver transplantation was conducted using a domino graft from a 4-year-old female child with Wilson's disease. After removing the right lobe of the FAP patient's liver, the graft was rotated 90 degrees counterclockwise and placed along the right side of the inferior vena cava(IVC). The orifices of the left, middle, and right hepatic veins were reconstructed using an iliac vein patch and then anastomosed to the right side of the IVC. Thirty days later, a second domino liver graft was implanted. The second domino graft was from a 3-yearold female child with an ornithine carbamyl enzyme defect, and it replaced the residual native liver(left lobe). To balance the function and blood flow between the two grafts, a percutaneous transcatheter selective portal vein embolization was performed, and "the left portal vein" of the first graft was blocked 9 mo after the second transplantation. The liver function indices, blood ammonia, and 24-h urinary copper levels were normal at the end of a 3-year follow-up. These two domino donor grafts from donors with different metabolic disorders restored normal liver function. Our experience demonstrated a new approach for resolving metabolic disorders with domino grafts and utilizing explanted livers from children.展开更多
The tetrahydroquinoline moiety is a structural feature of many natural products. By using a domino reaction of aromatic amines and cyclic enol ethers catalyzed by zirconyl chloride in water, various tetrahydroquinolin...The tetrahydroquinoline moiety is a structural feature of many natural products. By using a domino reaction of aromatic amines and cyclic enol ethers catalyzed by zirconyl chloride in water, various tetrahydroquinoline derivatives were synthesized efficiently. Most cyclized products showed cis selectivity. The cis selectivity was tentatively rationalized due to chelation control in water.展开更多
A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this techn...A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type leakage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 10.9% to 44.76% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 25℃ and 110℃ temperatures the maximum leakage power saving of 98.9% is achieved when compared to standard footerless domino logic circuits.展开更多
As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design f...As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27°C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.展开更多
文摘Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage comparator.NMOS is used to reduce stacking leakage as well as total exchange.Domino Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent years.In this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino circuit.The efficiency and effec-tiveness of the domino circuit are demonstrated through simulation results.The suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of power.The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR gates.As per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits.
文摘Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed. Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE. The simulation results show that the proposed circuits effectively lower the active power, reduce the total leakage current, and enhance speed under similar noise immunity conditions. The active power of the two proposed circuits can be reduced by up to 8. 8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage. At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4% ,respectively. Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.
基金the National High-Tech Research and Development Program of China(No.2005AA110020)~~
文摘An improved high fan-in domino circuit is proposed. The nMOS pull-down network of the circuit is divided into several blocks to reduce the capacitance of the dynamic node and each block only needs a small keeper transistor to maintain the noise margin. Because we omit the footer transistor, the circuit has better performance than the standard domino circuit. A 64-input OR-gate implemented with the structure is simulated using HSPICE under typical conditions of 0.13μm CMOS technology. The average delay of the circuit is 63.9ps, the average power dissipation is 32.4μW, and the area is l15μm^2. Compared to compound domino logic, the proposed circuit can reduce delay and power dissipation by 55% and 38%, respectively.
基金supported by the 2008 Scienceand Research Foundation of Hebei Education Department (No.2008308)
文摘A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper.Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also,a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.
基金Supported by Capital Special Program for Health Research and Development,No.2016-1-2021National Key Technologies R&D Program,No.2015BAI13B09+1 种基金The Training Program of Academic Leaders in Beijing Health System,No.2014-2-002Beijing Municipal Administration of Hospitals Ascent Plan,No.DFL20150101
文摘We report a case of double domino liver transplantation in a 32-year-old woman who was diagnosed with familial amyloid polyneuropathy(FAP) and liver dysfunction. A two-stage surgical plan was designed, and one domino graft was implanted during each stage. During the firststage, an auxiliary domino liver transplantation was conducted using a domino graft from a 4-year-old female child with Wilson's disease. After removing the right lobe of the FAP patient's liver, the graft was rotated 90 degrees counterclockwise and placed along the right side of the inferior vena cava(IVC). The orifices of the left, middle, and right hepatic veins were reconstructed using an iliac vein patch and then anastomosed to the right side of the IVC. Thirty days later, a second domino liver graft was implanted. The second domino graft was from a 3-yearold female child with an ornithine carbamyl enzyme defect, and it replaced the residual native liver(left lobe). To balance the function and blood flow between the two grafts, a percutaneous transcatheter selective portal vein embolization was performed, and "the left portal vein" of the first graft was blocked 9 mo after the second transplantation. The liver function indices, blood ammonia, and 24-h urinary copper levels were normal at the end of a 3-year follow-up. These two domino donor grafts from donors with different metabolic disorders restored normal liver function. Our experience demonstrated a new approach for resolving metabolic disorders with domino grafts and utilizing explanted livers from children.
文摘The tetrahydroquinoline moiety is a structural feature of many natural products. By using a domino reaction of aromatic amines and cyclic enol ethers catalyzed by zirconyl chloride in water, various tetrahydroquinoline derivatives were synthesized efficiently. Most cyclized products showed cis selectivity. The cis selectivity was tentatively rationalized due to chelation control in water.
文摘A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type leakage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 10.9% to 44.76% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 25℃ and 110℃ temperatures the maximum leakage power saving of 98.9% is achieved when compared to standard footerless domino logic circuits.
文摘As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27°C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.
