Fast Parallel Algorithm for Slicing STL Based on Pipeline

In Additive Manufacturing field, the current researches of data processing mainly focus on a slicing process of large STL files or complicated CAD models. To improve the efficiency and reduce the slicing time, a parallel algorithm has great advantages. However, traditional algorithms can＇t make full use of multi-core CPU hardware resources. In the paper, a fast parallel algorithm is presented to speed up data processing. A pipeline mode is adopted to design the parallel algorithm. And the complexity of the pipeline algorithm is analyzed theoretically. To evaluate the performance of the new algorithm, effects of threads number and layers number are investigated by a serial of experiments. The experimental results show that the threads number and layers number are two remarkable factors to the speedup ratio. The tendency of speedup versus threads number reveals a positive relationship which greatly agrees with the Amdahl＇s law, and the tendency of speedup versus layers number also keeps a positive relationship agreeing with Gustafson＇s law. The new algorithm uses topological information to compute contours with a parallel method of speedup. Another parallel algorithm based on data parallel is used in experiments to show that pipeline parallel mode is more efficient. A case study at last shows a suspending performance of the new parallel algorithm. Compared with the serial slicing algorithm, the new pipeline parallel algorithm can make full use of the multi-core CPU hardware, accelerate the slicing process, and compared with the data parallel slicing algorithm, the new slicing algorithm in this paper adopts a pipeline parallel model, and a much higher speedup ratio and efficiency is achieved.

A parallel pipeline connected-component labeling method for on-orbit space target monitoring

The paper designs a peripheral maximum gray differ-ence(PMGD)image segmentation method,a connected-compo-nent labeling(CCL)algorithm based on dynamic run length(DRL),and a real-time implementation streaming processor for DRL-CCL.And it verifies the function and performance in space target monitoring scene by the carrying experiment of Tianzhou-3 cargo spacecraft(TZ-3).The PMGD image segmentation method can segment the image into highly discrete and simple point tar-gets quickly,which reduces the generation of equivalences greatly and improves the real-time performance for DRL-CCL.Through parallel pipeline design,the storage of the streaming processor is optimized by 55%with no need for external me-mory,the logic is optimized by 60%,and the energy efficiency ratio is 12 times than that of the graphics processing unit,62 times than that of the digital signal proccessing,and 147 times than that of personal computers.Analyzing the results of 8756 images completed on-orbit,the speed is up to 5.88 FPS and the target detection rate is 100%.Our algorithm and implementation method meet the requirements of lightweight,high real-time,strong robustness,full-time,and stable operation in space irradia-tion environment.

Advances of Pipeline Model Parallelism for Deep Learning Training:An Overview

Deep learning has become the cornerstone of artificial intelligence,playing an increasingly important role in human production and lifestyle.However,as the complexity of problem-solving increases,deep learning models become increasingly intricate,resulting in a proliferation of large language models with an astonishing number of parameters.Pipeline model parallelism(PMP)has emerged as one of the mainstream approaches to addressing the significant challenge of training“big models”.This paper presents a comprehensive review of PMP.It covers the basic concepts and main challenges of PMP.It also comprehensively compares synchronous and asynchronous pipeline schedules for PMP approaches,and discusses the main techniques to achieve load balance for both intra-node and inter-node training.Furthermore,the main techniques to optimize computation,storage,and communication are presented,with potential research directions being discussed.

用于高速CIS的12-bit紧凑型多列共享并行pipeline-SAR ADC（英文）

设计了一款用于高速CMOS图像传感器的多列共享列并行流水线逐次逼近模数转换器。八列像素共享一路pipeline-SAR ADC,从而使得ADC的版图不再局限于二列像素的宽度,可以在16列像素宽度内实现。该模数转换器采用了异步控制逻辑电路来提高转换速度。半增益数模混合单元电路被用于对第一级子ADC的余差信号放大,同时被用于降低对增益数模混合单元电路中运放性能的要求。相关电平位移技术也被用于对余差信号进行更精确的放大。整个pipeline-SAR ADC第一级子ADC精度为6-bit,第二级子ADC为7-bit,两级之间存在1-bit冗余校准,最终实现12-bit精度。输入信号满幅电压为1 V。该8列共享并行处理的pipeline-SAR ADC在0.18μm 1P4M工艺下制造实现,芯片面积为0.204 mm^2。仿真结果显示,在采样频率为8.33 Msps,输入信号频率为229.7 kHz时,该ADC的信噪失真比为72.6 d B;在采样频率为8.33 Msps,输入信号频率为4.16 MHz时,该ADC的信噪失真比为71.7 dB。该pipelineSAR ADC的电源电压为1.8 V,功耗为4.95 mW,功耗品质因子(FoM)为172.5 fJ/conversion-step。由于像素尺寸只有7.5μm,工艺只有四层金属,因此这款12-bit多列共享列并行流水线逐次逼近模数转换器非常适用于高速CMOS图像传感器系统。

基于Pipeline的一类动态规划并行算法

动态规划是解决组合优化问题的有效方法之一．本文基于Ｐｉｐｌｉｎｅ结构，提出并分析了三个相似的动态规划并行算法（求简单最短路径．求最长公共子串和解背包问题）．获得了较理想的加速比、并行效率等指标．进而提出并讨论了这一类问题之动态规划并行处理的一般化思想及方法．

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

A parallel-pipelining software process model

Software process is a framework for effective and timely delivery of software system. The framework plays a crucial role for software success. However, the development of large-scale software still faces the crisis of high risks, low quality, high costs and long cycle time. This paper proposed a three-phase parallel-pipelining software process model for improving speed and productivity, and reducing software costs and risks without sacrificing software quality. In this model, two strategies were presented. One strategy, based on subsystem-cost priority, was used to prevent software development cost wasting and to reduce software complexity as well; the other strategy, used for balancing subsystem complexity, was designed to reduce the software complexity in the later development stages. Moreover, the proposed function-detailed and workload-simplified subsystem pipelining software process model presents much higher parallelity than the concurrent incremental model. Finally, the component-based product line technology not only ensures software quality and further reduces cycle time, software costs, and software risks but also sufficiently and rationally utilizes previous software product resources and enhances the competition ability of software development organizations.

A Practical Parallel Algorithm for All-Pair Shortest Path Based on Pipelining

On the basis of Floyd algorithm with the extended path matrix, a parallel algorithm which resolves all-pair shortest path （APSP） problem on cluster environment is analyzed and designed. Meanwhile, the parallel APSP pipelining algorithm makes full use of overlapping technique between computation and communication. Compared with broadcast operation, the parallel algorithm reduces communication cost. This algorithm has been implemented on MPI on PC-cluster. The theoretical analysis and experimental results show that the parallel algorithm is an efficient and scalable algorithm.

基于多绘制管线的大规模并行体绘制性能优化技术

针对数值模拟输出的大规模科学数据,体绘制方法为了刻画复杂物理特征,会进行高密度光线采样,但由此带来了极大的计算开销和数据增量。在国产自主CPU高性能计算机上,由于处理器单核的计算能力低于商业CPU,只能使用更多的处理器核来分担体绘制任务,从而引起了采样数据并行通信的可扩展性瓶颈。为充分利用国产自主CPU高性能计算机来高效完成体绘制任务,针对大规模并行体绘制提出一种基于多绘制管线的性能优化技术,通过多管线、多进程的两级并行模式来降低单条管线的并行规模。在大规模并行体绘制中,该技术将绘制目标图像划分成多个子区域,绘制进程则相应分组,每个进程组独立执行一条绘制管线,以完成图像相应子区域的绘制,最后再收集所有的图像子区域,形成完整图像并输出。实验结果表明,优化后的体绘制算法在国产自主CPU高性能计算机上可以扩展到万核规模,并能有效完成体绘制任务。

长输原油管道并管混输运行方案研究

为实现长庆油田第三输油处姬惠线和油惠线不加降凝剂和减阻剂运行,实现节能降耗,通过建模仿真,开展并管混输运行模式研究。首先,建立管网仿真模型,利用现场近5年历史数据进行模型调试与校验,使模型精度达到95%以上,能够准确描述现场的水力和热力特征;然后,分析并管混输后的管道沿线水热力分布,结合各站场设备和管线情况,研究并管混输的可行性;接着,通过控制边界条件,模拟分析并管混输的输量和温度控制范围。最后,进行现场试验验证,对比分析理论与实际。结果表明:姬惠线通过姬马复线或新建联络线分输一部分原油至油惠线,均可实现姬惠线不加减阻剂、油惠线不加降凝剂运行;根据输油计划,最大可分输320 m^(3)/h,最小需分输182 m^(3)/h,冬季最低出站温度为57℃,与并管混输前相比,可降低33℃;经过现场试验与应用,研究结果与现场运行结果一致,实现了节能降耗。

面向微控制器的卷积神经网络加速器设计

针对目前嵌入式微控制器的性能难以满足实时图像识别任务的问题,提出一种适用于微控制器的卷积神经网络加速器。该加速器在卷积层设计了无阻塞的行并行乘法-加法树结构,获得了更高的硬件利用率;为了满足行并行的数据吞吐量,设计了卷积专用SRAM存储器。加速器将池化和激活单元融入数据通路,有效减少数据重复存取带来的时间开销。FPGA原型验证表明加速器的性能达到92.2 GOPS@100 MHz;基于TSMC 130 nm工艺节点进行逻辑综合,加速器的动态功耗为33 mW,面积为90 764.2μm^(2),能效比高达2 793 GOPS/W,比FPGA加速器方案提高了约100倍。该加速器低功耗、低成本的特性,有利于实现嵌入式系统在目标检测、人脸识别等机器视觉领域的广泛应用。

煤干馏用多个并联分离器结构优化

针对原并联分离器入口管路和升气管出口管路堵塞等问题,研究了煤干馏过程中并联旋风分离器入口管路、升气管出口管路结构型式对管路内流体的影响,对结构进行了优化,并与原结构进行了对比。结果表明:通过在入口管路增大弯头角度以及减少弯头个数,能有效降低管路整体压降,相比原管路结构,优化后管路压降下降约为75%;采用三通管可防止弯头外壁侧气速较低,避免颗粒在低速区沉积并发生堵塞;采用切入式升气管可有效改善排气管内由于旋流导致的低速区以及不稳定流动问题,能够避免颗粒堆积;通过延长盲端管路高度可有效减少涡流对分离器流场的影响,综合流场以及压降分析,升气管的盲端高度为700 mm时最为适合。工业上整体系统运行周期从3个月延长至6个月以上,相比原结构,压降降低约48%。研究可为并联旋风分离器在工程上的设计和应用提供指导。

基于国产异构FPGA的空中红外目标检测跟踪系统

随着国产器件在各领域的大力推广及应用,针对高帧频、强实时性光电系统空中红外目标捕获引导问题,介绍了一种基于国产异构FPGA的空中红外目标检测跟踪系统架构及其实现方法。基于AXI4总线协议,采用模块化设计及软硬件协同处理方法,构建系统架构和视频流水线;并行流水处理实现中值滤波,通过加权二维空间滤波流水处理实现基于背景抑制的快速空中目标检测,与中值滤波一起部署于FPGA逻辑资源(PL);检测结果实时传输到部署于FPGA处理器端(PS)的空中目标跟踪模块,完成目标跟踪,PS完成系统所有功能模块的控制;跟据各功能模块串/并行实现方式,统筹部署完成整个异构系统设计。实验结果表明,该系统能够实现1 280×1 024@100 Hz红外视频空中目标的实时检测及稳定跟踪,系统资源占用率小于25%,时延小于2帧,可满足高帧频、强实时性光电系统要求。该系统的实现是国产自主可控异构FPGA核心芯片工程应用的一次重要探索。

基于FPGA改进的Canny算法边缘检测系统

针对Canny算法在图像边缘检测中的限制,包括自适应性差、边缘信息易丢失和处理时间过长等问题,提出了一种基于FPGA的模块化硬件设计,用于实现改进型Canny算法的高效边缘检测。首先,利用FPGA的数据并行处理特性,采用快速自适应中值滤波算法替代高斯滤波方法;其次,引入3×3模板替代2×2模板,并在45°和135°方向上增加计算模板,以获取图像的梯度和幅值信息;最后,结合Otsu原理,采用三阈值连接来增强自适应性,减少图像边缘信息的丢失。经过实验验证,该系统展现出良好的自适应性能,有效处理图像中噪声的同时,能够捕捉到有效的边缘特征,并具备高速、实时等特点。

西南山区并行油气管道阴极保护系统之间的干扰因素与规律

以西南山区并行油气管道阴极保护系统之间干扰为研究对象,采用BEASY软件模拟计算了多种因素对管道阴极保护系统之间干扰的影响,并通过现场跨接缓解管道干扰。结果表明:并行管道阴极保护系统间的干扰随管道并行间距的增大呈逐渐减小的趋势;当受干扰管道的涂层破损率较大时,管道电位负向偏移明显;并行管道阴极保护系统间的干扰程度随土壤电阻率的增大而增大,且电位偏移呈边界递减趋势;跨接能有效提升阴极保护水平较差管线的保护效果,降低并行管道之间的干扰程度。

新疆油田并行管道阴保系统相互干扰因素及规律

针对新疆油田多条管道并行敷设产生的阴保系统相互干扰问题,采用数值模拟技术,研究土壤电阻率等8个因素对并行管道干扰程度的影响规律。结果表明:随着土壤电阻率或干扰管道涂层破损率增加,被干扰管道近阳极端电位负移,远阳极端电位正移,干扰显著增强;随着管道间距增加,干扰程度略有增加后逐渐降低,且最强干扰管道间距随土壤电阻率和涂层破损率增加而增大;随着干扰管道直径增大,或当干扰管道为高温管道时,并行管道受干扰略微增强;随着干扰管道辅助阳极距离增加,干扰减弱,但当辅助阳极距离小于200 m时干扰影响仍较为显著;当辅助阳极位置分别在两条并行管道一侧或两侧分布时,并行管道受干扰程度均较小;随着干扰管道数量增多,干扰电流存在明显叠加效应,干扰程度显著增强。综上,土壤电阻率、涂层破损率及干扰管道数量是阴保系统相互干扰的主控因素,管道间距、辅助阳极距离影响次之,辅助阳极相对位置、管道类型、管道直径影响较小。

某双管同沟敷设管线阴极保护系统干扰防护数值模拟研究

为明确同沟敷设管道阴极保护系统相互干扰规律及干扰防护措施,以新疆油田某双管同沟敷设管道(D219和D457)为模型,设置D219管道的涂层破损率为0.1%,D457管道的涂层破损率为0.1%、0.5%、1.0%,采用数值模拟方法对不同阴极保护设计及阴极保护干扰防护措施的有效性及适用性进行评估。结果表明:采用浅埋阳极单独阴极保护的同沟敷设管道存在阴极保护系统相互干扰,随着干扰管道D457防腐层破损率的增加,其对并行管道D219的干扰程度增强,施加均压线措施可有效降低干扰;采用浅埋阳极联合阴极保护+均压线措施可消除同沟敷设管道阴极保护系统的相互干扰,当双管同沟管道防腐层破损率相差较大(D2190.1%,D4571.0%)时,改善效果较为显著;对于采用深井阳极联合阴极保护的同沟敷设管道,当D457防腐层破损率较大(1.0%)、土壤电阻率较高(50Ω·m)时,其阴极保护效果较差,采用均压线+牺牲阳极措施对阴极保护效果的改善作用不明显,而增大深井阳极输出电流联合均压线措施可显著改善同沟敷设管道的阴极保护效果。

新疆油田并行管道阴保系统相互干扰防护措施适用性研究

针对新疆某油田多条并行管道阴保系统产生的直流杂散电流干扰问题,采用数值模拟方法对不同阴极保护设计和排流保护方法的治理效果及适用性进行了评估。结果表明:对于新建并行管道,阴极保护站分建(阳极地床位置交错分布)措施可消除并行管道与阴保系统相互干扰,改善阴极保护效果;对于防腐层破损率较小(<2%)的在役并行管道,可在并行管道阴极保护电位差值最大处施加均压线措施降低干扰;对于防腐层破损率较大(>2%)的并行管道,不推荐深井阳极+均压线联合阴极保护措施;对于在低土壤电阻率(<100Ω·m)环境中运行的在役并行管道,牺牲阳极排流保护措施可有效降低干扰;对于高土壤电阻率(≥200Ω·m)、高防腐层破损率(≥5%)的在役并行管道,减小阴保站(阳极地床)距离可降低干扰。

相控阵快速波束控制算法设计与FPGA实现

相控阵天线的电扫描特性使其具有扫描灵活、指向精确、可靠性高和抗干扰能力强等特点,其实现波束快速扫描、波束形状快速变化、同时多波束快速形成能力的关键技术之一是波束控制技术。针对多波束多阵元波束控制快速响应的需求,对常规单波束控制算法进行分解和优化,提出单波束内基于截断归一化的流水线设计算法、多波束并行计算方法,来进行移相控制码计算。该算法完成单波束内N个阵元的移相码计算仅需(N+12)T(其中T为系统工作时钟的周期,典型值为8 ns),可快速计算各天线阵元所需移相控制码。所提方法较传统单波束移相控制码计算方法时间缩短一个数量级以上,并已在FPGA上得到实际验证与应用。