This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structur...This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.展开更多
The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock ...The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.展开更多
文摘This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
文摘The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.
